Design of AND Gate Schematic in Cadence Virtuoso

[@RIYAYADAV-i6f4m]

Great explanation. Thankyou very useful 🎉

[@CadenceVLSI]

Thank You!

[@smeetchandra3762]

Nice trick mam in my software ,other methods are not working but suddenly I tap your video and boom 💥 your trick works for my software , thanks 🙏

[@CadenceVLSI]

Thank You!

[@RoshanKumar-vf4tt]

Mam can you make video on 3 input AND gate?

[@CadenceVLSI]

ruclips.net/video/aKcnyKXdoDo/видео.html

[@karanchoudhary5652]

Why their is a spike in the output waveform

[@CadenceVLSI]

When both the inputs are 1 we generally see these spikes, this happens when the inputs are not perfectly synchronised and when there is a slight delay in one input.