Hats off to you sir. Wonderful teaching.. I've referred multiple text books for digital electronics including d reference books and found many concepts contradicting. But ur explanation provides a one stop solution to all my doubts. Thanks a million sir.
Really Effective videos on Digital Electronics. Easily described. Must watch for the ones who want to learn Digital Electronics. Eagerly waiting for the next ones.
Many many thanks to you sir.....M feeling very confident now, I have seen the complete digital electronics lecture and M also able to solve gate problems.THANK U SOO MUCH NESO ACADEMY 😊😊💝
amazing work.. helped me aloooott.. have my exam tomorrow. was struggling sooo much for this going frm ppts n books n notes but u jus made it soooo easy.. in jus a few minutes.. amazing.. great work.. n thanks alooooot.... keep up the good work.. :) (y)
Sir if we want to store 1 0 0 0 (you ment this in 9:59) how we can rewrite 0 0 for last 2 flip-flops. Because if clock is zero D is don't care. I think both flip flop outputs remains 1 in this case becuase of D is dont care.
Hello good sir, can you please clear me on why is it a good practice to increase the D to high just before the first clock pulse and not keep it high from the beginning?
In pipo if I want to enter one more data we need to make as clk high . After entering the data clk make it as low . It will be stored in buffer . So it is also called as buffer register
I have a doubt.. In SIPO form, only in more than 4 clock pulses, Q0 will become 1.. Till the it will be like : 0000, 1000, 1100, 1110 and then only 1111?
Sir, why do we need to convert D3=1; D2=0; D1=1; D0=1 before the occurring of negative edge clock pulse? it should be at the point of occurring of the pulse. why do we change it before? You said that "It is a good practice".. but why?
It is to ensure that the inputs are set to the right values before the FF is activated. In this way, we reduce the chance of errors. Would it be nice that the food be prepared nicely before eating it?
Initially the reference is taken as zero i.e every state start with zero,if u don't change those D3,2,1,0 before they encounter negative edge,we ll get zeros as output as d flip flop gives input as output
if some lag will occur in transferring data(input) at right moment then we will give wrong input to FF and as a result may get wrong output so it will be better to set the input bits before the negative edge is encountered(FF becomes active). your question is a year ago...so i am late to answer but i am doing it for ones who have doubts now can take reference from this.
In PIPO we made the D0 as 1 before the negative trigger..... But if the negative trigger arrives then the 1 becomes 0 and the value stored will be the complement of the input... I'm totally confused with this. Please 🙏 clear my doubt
initially u explained that in SISO we need more clock pulses to get the data but data is stored in 4 clock pulses. In order to get out the stored data we need to complete the cycle .Can we give any input of our choice after 4 inputs ??
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This lecture was uploaded 6 year ago still it's helping us a lot 🌞🌞
8*
Now it's 8 year's
8
9 year
This comment was uploaded 3 years ago still it relates
its 8 years of uploading this video and no another can give competition to this content.❤
Evergreen lectures......🔥🔥🔥🔥🔥 Thanks Neso Academy....
Yes, very good lecture.....
Aptly titled comment. 7 years later there are still people watching this and finding out that it is the most relevant playlist out there.
5 years ago and still helping me...!👏👏👏👌👌👌 great workkk ❤️✨❤️
Yes very good class...
This channel is a saviour of students🙇♀️🙇♀️
Amazing!!
You are truly a life savior, we need more people like you who can teach such difficult concepts in such a comprehensive way!
Yes Sarvesh, very good lecture.....
7 saal beet gaye aapke iss comment ko...Abtak toh job lag gayi hogi na :)
I like how you put these videos only one month before we discussed them in class. I feel lucky.
what are you doing in your life now bruhhhh???!
@@chandramohan9531 YES I wanna knoww!!
one of my friends frm clg recommended me this channel ..One of the best recommendations i hv recieved in a while ...a very nice way of teaching
Hats off to you sir. Wonderful teaching.. I've referred multiple text books for digital electronics including d reference books and found many concepts contradicting. But ur explanation provides a one stop solution to all my doubts. Thanks a million sir.
thank you so much sir..
Ur tutorials have helped me a lot, even more than my college lecturers.
You are right friend....
whatcha doin now brah?
Really Effective videos on Digital Electronics. Easily described. Must watch for the ones who want to learn Digital Electronics. Eagerly waiting for the next ones.
Sir, your lectures helped so much. I went through many of them and now I've got quite a clear idea about these counters. Thank you very much.
Many many thanks to you sir.....M feeling very confident now, I have seen the complete digital electronics lecture and M also able to solve gate problems.THANK U SOO MUCH NESO ACADEMY 😊😊💝
Uploaded before 8 years and still helping us ❤
Godlike teacher . Covered 2 months of college stuff in 2 days before exam .
Electrical engineers attendance lgwao
Thank you very much sir you give such a good lecture that anyone can understand. We pray for you that god live you Long.
Your Classes are very Conceptual and Understandable .
amazing work.. helped me aloooott.. have my exam tomorrow. was struggling sooo much for this going frm ppts n books n notes but u jus made it soooo easy.. in jus a few minutes.. amazing.. great work.. n thanks alooooot.... keep up the good work.. :) (y)
Really amazing lectures 😍🔥
Thanks a lot . Please teach at our college :P
hahaha, a valid conclusion.
Which college?
My professor didn't explain shit, i don't understand how some of my college professors get hired
which college?
@@kushwanthkapa2041 darbhanga college
mine too!!!
same
big mood
Thank u sir :) apke Regular students to bohot lucky h yaar
You teach really well😍
Sir your videos are really realy helpfull. Thanks a lot for making such videos. Sir, Can you please make videos on MEMORY DEVICES? Thank you sir
thank you for this explanation. cleared so many of my doubts Sir.
Once i finish my engineering and start earning,.. i am gonna donate you a lot of money
Yes friend he deserve it....
Did you finish ?
Your lectures helped so much 💻
hi sir...iam vasanth..its really a gud explanation for all the topics which u hav done so far....iam really grateful to u...keep it up.mm
This lacture uploaded 8 year ago still helping us
If we have any doubt s or confusion we have clear thought that neso academy in our mind.. tension free..
We should consider the positive edge( Rising Edge ) instead of falling edge
Please do include this video in Shift Register Playlist...superb explanation
Very good presentation, congrats!
SIR THANK YOU...and please add lectures of digital logic families : RCL, DCTL, DTL, TTL etc...
Thank you!! These are great videos, they helped me a lot
Thank you NESO ACADEMY..I would like to see your face soon 😊
Yes nice videos, right?
A completion if I may : A register is a group of flip-flops which have the same Clock ( mostly D flip flops, maybe there are also JK one's )
Exactly....
sir please add lecture of digital logic families RCL,DCTL, DTL, TTL etc.
Yep
Sir if we want to store 1 0 0 0 (you ment this in 9:59) how we can rewrite 0 0 for last 2 flip-flops. Because if clock is zero D is don't care. I think both flip flop outputs remains 1 in this case becuase of D is dont care.
This guy is on another level...
Very well taught Sir.Thank You
6years ago, still helped
Thank youu so much ❣️neso
One hour before exam!!!!
Can someone tell me why at @9:45 when the clock =1 , 1011 goes to 1000?
9 years and and still stealing the show😍
sir will you post the remaining videos regarding registers i mean universal registers
Advanced congratulations for 1M
where can i get these notes someone please tell me
Shouldn’t you change the D before the rising edge arrives? Doesn oitput change only when the rising edge comes?
It was really helpful for my sem final
Very wonderful presentation sir....
Thank you so much
Hello good sir, can you please clear me on why is it a good practice to increase the D to high just before the first clock pulse and not keep it high from the beginning?
Very very thank you sir
Your lecture is very nice
2021 Dec 9 ❣️❣️it's been Soo helpful
Nostalgia 😢 after hearing 2021
Love you neso acedmey❤❤
there are very helpful vedios on neso acadamy
ur class r very gud . i will following all of ur classes. tanq so much
dear sir,which one is easy for our purpose in using either SIPO OR PIPO?
That depends on the application....
Thanks sir this lecture has help me so so so much thanks again
Where is the load (needed to store data in regester) that you mentioned in the previous presentation of introduction to register ?
It feels really uncomfortable to be a physics student among the engineering students in the comments section 😂
You have a very good voice.
What is the use of clock 0 and clock 1 in PIPO?
In pipo if I want to enter one more data we need to make as clk high . After entering the data clk make it as low . It will be stored in buffer . So it is also called as buffer register
Yes, you are right....
love you sir..
your video is so effective
for Me..
Uh r really doing amazing job
Thanks a lot sir
Thanks for teaching sir! It helped me a lot
tomorrow i have my exam.... cant believe i completed 202 videos in one night....proud on myself
202 videos in one night😮😯😳
Why u started drawing the clock pulse before the falling edge starts in PIPO register
it's very important for us thanku sooo much.......................
1 day before exam😊
In morning time of exam day😂
In the PIPO Shift regester If we give the clock as 1 in this case we will still be getting the same output as that of the inputs ......
I have a doubt.. In SIPO form, only in more than 4 clock pulses, Q0 will become 1.. Till the it will be like : 0000, 1000, 1100, 1110 and then only 1111?
Does this store and output the data in single clock pulse or it just stores in a single clock pulse?
Great work sir !!!!!
Please upload videos on logic families ...........
Thank you once again , keep up the good work.
bhot hi bdiyaaaaaa👏🏻👏🏻👏🏻👏🏻👏🏻
I have dought that , if we can ragister an input bit we cannot change it or put another
thanks for such a good explanation sir
Requesting you to teach Electromagnetic theory....... 🙏
We should always in pipo put the clk zero to store ? What about the bubble?
As we have to keep clock = 0 to store the data in SIPO then how we need 1 clock pulse to store data in SIPO? as you said in the video.
Sir, why do we need to convert D3=1; D2=0; D1=1; D0=1 before the occurring of negative edge clock pulse? it should be at the point of occurring of the pulse. why do we change it before? You said that "It is a good practice".. but why?
don't ask anything, the teacher always right
It is to ensure that the inputs are set to the right values before the FF is activated. In this way, we reduce the chance of errors.
Would it be nice that the food be prepared nicely before eating it?
Initially the reference is taken as zero i.e every state start with zero,if u don't change those D3,2,1,0 before they encounter negative edge,we ll get zeros as output as d flip flop gives input as output
if some lag will occur in transferring data(input) at right moment then we will give wrong input to FF and as a result may get wrong output so it will be better to set the input bits before the negative edge is encountered(FF becomes active).
your question is a year ago...so i am late to answer but i am doing it for ones who have doubts now can take reference from this.
Please make videos on logic families
In PIPO we made the D0 as 1 before the negative trigger..... But if the negative trigger arrives then the 1 becomes 0 and the value stored will be the complement of the input... I'm totally confused with this. Please 🙏 clear my doubt
I MEAN WHICH MODE IS BETTER FOR USING (SIPO OR PIPO)
Thank you bro....😃😍👌
Good work...👍
7:50 why we make d3 high before clock pulse arrive
initially u explained that in SISO we need more clock pulses to get the data but data is stored in 4 clock pulses. In order to get out the stored data we need to complete the cycle .Can we give any input of our choice after 4 inputs ??
Thank alot sir ❤️
Very nice video, isn't it?
good work sir u helped me a lot
sir please upload videos on logic families.i am facing difficulties in understanding that chapter and also the operation of universal shift registers.
How Din should be drawn??
sir, how to implement the same logics using any other flip flops(i mean j-k or s-r)..
how to design a 5-bit shift register that can be used for any of the four modes of a shift registers
This is really nice.please provide pipo full timing diagram.
الله يفتح عليك يعم
Why is that only one clock pulse is required to store data in pipo
will you please make some real time examples where do we use the registers....?