I would like to ask if you can share your knowledge/material that goes in depth on the mathematical modeling of piezoelectric energy harvesters. What structures could generate power at least 1uW at very low frequencies? Im writing a thesis using piezoelectric on pacemaker
During the parallel loading, pin 0 of the right most MUX won't come into picture. Because the input at pin 3 will appear at the output. I hope you got the answer. In case, if you still have any doubt then let me know here.
As of now, the playlists/ series are there based on the topics and subjects. But yes, in future, will make the series based on the specific engineering year.
4:59 have you applied the negative edge trigger to clock 2 signal i.e., upper register Coz. You said between 4 th and 5 th clock pulse we will get the output in the upper register.. Reply soon bud.
You can apply the clock to the upper register once the data in the lower register is settled. (After the settling time) So, here the clock to the upper register is applied between the 4th and 5th clock pulse. In this case, it happens to be after the falling edge of the 4th clock cycle.
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For videos on Digital Electronics, check this playlist:
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thought this topic was quite difficult but your method of explanation made this topic a cake walk
These videos helped me pass my electronics class, thankssss😆
Thanks for the infotainment
Absolutely nice 👍👍
Awesome as usual.
Very nice 👌👌
mauj kra diye bhaiya ji kal ke exam mein aag lga denge
I would like to ask if you can share your knowledge/material that goes in depth on the mathematical modeling of piezoelectric energy harvesters. What structures could generate power at least 1uW at very low frequencies?
Im writing a thesis using piezoelectric on pacemaker
Sir at 16:29 i.e during Parallel load of universal shift register what is the use of pin 0 of the rightmost mux, i mean what input is given to that ?
During the parallel loading, pin 0 of the right most MUX won't come into picture. Because the input at pin 3 will appear at the output.
I hope you got the answer. In case, if you still have any doubt then let me know here.
@@ALLABOUTELECTRONICS Sir but then why in 15:54 the pin 0 on the rightmost mux connected with the output of the FF 4?
Sir, I didn't understand why we made the SIPO register like that, what was our primary goal of doing it?
Hello, will there be a course/series based on ece/ee/eee/in for students, based on 1st, 2nd and 3rd and 4th year pls..
As of now, the playlists/ series are there based on the topics and subjects. But yes, in future, will make the series based on the specific engineering year.
4:59 have you applied the negative edge trigger to clock 2 signal i.e., upper register
Coz. You said between 4 th and 5 th clock pulse we will get the output in the upper register..
Reply soon bud.
You can apply the clock to the upper register once the data in the lower register is settled. (After the settling time) So, here the clock to the upper register is applied between the 4th and 5th clock pulse. In this case, it happens to be after the falling edge of the 4th clock cycle.
👌👌👌👍👍👍
Thanks!
Thank you, I really appreciate your support.
Why not parallel in serial out in shift left????