Xilinx ILA Demo using Vivado 2020, Vitis, and Avnet Minized rev1

[@sehsamudra]

Very nice! Just what I wanted to read up this weekend.

[@ee_tech_channel6148]

Very good and clear explanation. Thanks. Hope you will make more exercises like this. Very helpful :)

[@mrfiedler7616]

Thank you for this very good demo

[@JhovannyUribe]

Thank you for your demo, well explained

[@giancarlokuosmanen9723]

Cheers for your awesome tutorial!

[@nikolaykostishen6402]

Thanks!

[@EngineerAnandu]

Please upload more vids

[@teeamoansbach3327]

The sound is very low

[@hiteshb5606]

What to do if I want to monitor axi signals?

[@soulcatcher7854]

Why did you run VITIS here? It was not necessary to show the use of ILA.

[@oliverpeters6944]

He uses the Zynq processing clock (FCLK_CLK0 and FCLK_CLK2) to drive the counter and the ILA. Therefore he has to start the Zynq processor to configure and start the clocks. This is done by running the debugger in Vitis.