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Thank for the video. When I try I don't see any of my probes in the waveform window.

Hi... I am getting an error while i tru to debug launch hardware as: Error while launching program. Cannot reset APU. APB AP transaction error, DAP status 0xF0000021.... Kindly suggest me some solutions to resolve this...

Dear Sir I have built a module using PL part only to calculate the summation of Bytes. Now, I try to use the Zynq with axi-gpio to read the final value of the summation. I test each circuit individually, it is works correctly. The problem is that when I connected them together (the PL with PS), I did not get any results by the Zynq at the serial monitor. Please, if you can help. Thanks.

@marwanal-yoonus280 0 seconds ago Dear Sir Please, I have a problem during reading the status of an output switch on Zybo Z7-10. I use Vitis to program the Zynq processor with Gpio connected to a slid switch. I make the switch (input2) status as a condition as shown in the program below if (D == 1) ; The following program works only when the input2 signal that was connected to Gpio IP starts from ("1") but the program does not work when input2 signal starts from ("0"). ////////// while (1) { D = XGpio_DiscreteRead(&input2, 1); // input2 from a slide switch if (D == 1) { sum_all = XGpio_DiscreteRead(&input, 1); // input is a 32-bit data printf("%x " , sum_all); sleep (1); } else { XGpio_DiscreteWrite(&output, 1, 0); // output is a LED printf("No_Signal "); sleep (1); } } ///////////// i.e. the program works only when I change input2 from "1" to "0" but does not work when the input2 start changes from "0" to "1".

@marwanal-yoonus280 0 seconds ago Dear Sir Please, I have a problem during reading the status of an output switch on Zybo Z7-10. I use Vitis to program the Zynq processor with Gpio connected to a slid switch. I make the switch (input2) status as a condition as shown in the program below if (D == 1) ; The following program works only when the input2 signal that was connected to Gpio IP starts from ("1") but the program does not work when input2 signal starts from ("0"). ////////// while (1) { D = XGpio_DiscreteRead(&input2, 1); // input2 from a slide switch if (D == 1) { sum_all = XGpio_DiscreteRead(&input, 1); // input is a 32-bit data printf("%x " , sum_all); sleep (1); } else { XGpio_DiscreteWrite(&output, 1, 0); // output is a LED printf("No_Signal "); sleep (1); } } ///////////// i.e. the program works only when I change input2 from "1" to "0" but does not work when the input2 start changes from "0" to "1".

I have a question re: minute 20:00. You have got your board plugged in... How is it plugged on? How is the Hello World app downloaded to the board? Over USB/UART? Over Ethernet, where the so called agent on the remote board grabs the files sent and places them in a specific location and runs the app? Over JTAG interface? Cheers

Please upload more vids

good video, but it doesn't tell about licensing - I changed the chip to Kintex UltraScale XCKU15P and it says I don't have license for HLS synthesis

Is it work with picorv32 with some interconnect and peripherals ?

I want to recive gps data through uart on zed board. how to do that?

What to do if I want to monitor axi signals?

When attempting to Validate the Design, I keep getting the error ' [BD 41-758] The following clock pins are not connected to a valid clock source: /processing_system7_0/M_AXI_GP0_ACLK'. Any ideas?

Hi, what's your gmail account? I wanna contact you. Thanks

Thanks!

FYI this video was copied by another channel, and only the copyright owner can report them: ruclips.net/video/7aRxSqfnExU/видео.html

Very helpful. Thank you.

Thanks so much for making this!!! I'm a complete n00b, but you got me started.

hello, thank you for the tutorial! i keep having a problem when trying to create the hello world application. when i select the "Hello World" example, i get the following message: "This application requires a Uart IP in the hardware." i am using zybo 7z010 board. what am i doing wrong? should i add at the beginning a UART ip core in vivado block diagram or something like that?

Thankyou very much, this video was extremely helpful.

@15:08 you Browsed your project folder for your design_1_wrapper.xsa file and it successfully opened with Operating System: standalone and Processor: ps7_cortexa9_0. Well, when I selected my design_1_wrapper.xsa file it took a while BUT both the Operating System and Processor were greyed out and blank. It would not let me continue. So, can I select a default XSA and which one? Or do I need to go back and fix something? Note: since my free Vivado 2021.2 ML Version failed with the MiniZed board I had to substitute the Zybo Z7-20 (xc7z020clg400-1) board, Report IP status, Upgrade Selected, Generate the Output products which worked, Run Synthesis, Implementation, and Generate Bitstream successfully, Export the Bitstream file to Target HW, selected Zybo Z7-20's XSA file created in my project folder, Exported HW Platform. Then I opened Vitis Tools > Launch Vitis IDE > Create New Platform > hello_world_platform > XSA File: design_1_wrapper.xsa > Open > Reading HW specification. Software specification: Operating System: <blank> greyed out Processor: <blank> greyed out Aby suggestions on how to remedy this problem? After further investigation, it appears you skipped a few steps in Synthesis because you did not use a MiniZed board Constraints file and did not set the I/O pins for this design application. So, go the following critical warnings: General Messages [Common 17-55] 'set_property' expects at least one object. ["c:/Users/..../Documents/Xilinx/FPGA/Projects/RobertSwan/Hello_world_microzed/Hello_world_microzed.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc":33] [Vivado 12-1411] Cannot set LOC property of ports, Could not legally place instance design_1_i/processing_system7_0/inst/genblk13[31].MIO_BIBUF at E16 (IOPAD_X1Y108) since it belongs to a shape containing instance design_1_i/processing_system7_0/inst/PS7_i. The shape requires relative placement between design_1_i/processing_system7_0/inst/genblk13[31].MIO_BIBUF and design_1_i/processing_system7_0/inst/PS7_i that can not be honoured because it would result in an invalid location for design_1_i/processing_system7_0/inst/PS7_i. ["c:/Users/.../Documents/Xilinx/FPGA/Projects/RobertSwan/Hello_world_microzed/Hello_world_microzed.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc":188] Design Initialization [Common 17-55] 'set_property' expects at least one object. ["c:/Users/.../Documents/Xilinx/FPGA/Projects/RobertSwan/Hello_world_microzed/Hello_world_microzed.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc":33] [Vivado 12-1411] Cannot set LOC property of ports, Could not legally place instance design_1_i/processing_system7_0/inst/genblk13[31].MIO_BIBUF at E16 (IOPAD_X1Y108) since it belongs to a shape containing instance design_1_i/processing_system7_0/inst/PS7_i. The shape requires relative placement between design_1_i/processing_system7_0/inst/genblk13[31].MIO_BIBUF and design_1_i/processing_system7_0/inst/PS7_i that can not be honoured because it would result in an invalid location for design_1_i/processing_system7_0/inst/PS7_i. ["c:/Users/.../Documents/Xilinx/FPGA/Projects/RobertSwan/Hello_world_microzed/Hello_world_microzed.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc":188] So, do you have a recommended I/O Ports for the following this applications (86) signals? Thanks, JT

And if I don't want to use an IP? To just write VHDL and synthesize that (after providing a target chip of course)?

Does Vitis HLS v2022.1 support built-in HLS Functions such as hls::Threshold, hls::Erode, hls::Dilate, hls::Mul, hls::Duplicate, hls::MinMaxLoc, hls::CvtColor etc. ?

Thank you for this very good demo

Thanks for your video, very usefull! Do you know the reason for Xilinx to switch SDK yo Vitis? It seems pritty much the same thing...

Very nice! Just what I wanted to read up this weekend.

Thank you so much for this! I've had a look through at least 5 different tutorials until I saw yours and finally made my board do something!

Great Tutorial. I Have some questions as I have recently purchased a KV260 board and am trying to port my code onto it. Do you have a discord where I can hit you up?

It is very helpful. Are you able to put together a video to show us how to utilize the GigiEnthernet on the board the Zynq board and use the Ethernet board to transmit data to another computer? Thank you for your time!

Hi. can I ask where did the M_AXI_GPO_ACLK go??

You should have included a GPIO component in the tutorial so it would be even better!

why are there 2 board support packages in the video?

This is just the video I need to figure out simply how vivado and vitis cooperate. Thank you very much.

This should be a template for all instructional videos that try to address complex tools like Vivado and Vitis. Xilinx has a lot to learn when it comes to making videos explaining their tools to beginners, IMO. Thank you very much.

Cheers for your awesome tutorial!

The sound is very low

I’m using a Cora Z7 board and when I run the auto router in the block diagram it throws an error that the clk input is not connected to a valid source. The block diagram didn’t change the way yours did. Any idea what it could be?

You keep referring to IP. Internet Protocol? Intellectual Property?

Hello sir,thanks for the video,how to work with lwip tcp server client application vitis in qemu emulator?if possible please tell us the procedure.

is there a tutorial to do this for linux platform, i keep getting a sd card error

When it comes to actual hardware, how does C interact with the "hardware"? When I build something using vivado, where can I output/input 1/0 using C/Vitis?

Robert great video tutorial, thanks. :)

Why did you run VITIS here? It was not necessary to show the use of ILA.

Unable to create firmware project...

First tutorial so far that I could follow all the way through and everything works. Thanks for the video!

Much Appreciated!! Helped me with Udemy Course 'Learn Fundamentals of FPGA and VHDL Development; Lecture 70

Thank you so much for this tutorial, I've been completely clueless on how am I supposed to work with it and had no idea where to start. This tutorial was an incredible starting point and I'm very grateful I stumbled upon it.

Excellent!

Hello, thanks for the video. Can you explain what are the differences between Xilinx SDK and Vitis ?

quick and very informative, thanks mate

I want to print hello world on third party simulator Xcelium which is available in vivado.. can you please tell me how to do that? Or can you provide me with any tutorial to do so?