Compiler directive & System tasks in Verilog | #14 | Verilog in English

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  • Опубликовано: 12 сен 2024
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    #vlsipoint #verilog #VLSI #HDL #verilog_in_english
    #System_tasks
    #Compiler_directives
    #Internal_variable_monitoring_system_task
    #Simulation_control_tasks
    #Simulation_time_related_tasks
    System tasks (ST)
    1. Internal variable monitoring ST
    2. Simulation control Tasks
    3. Simulation time related Tasks
    There are tasks and functions that are used to generate input and output during simulation. Their names begin with a dollar sign ($).
    1. Internal variable monitoring ST
    $display
    $write
    $strobe
    $monitor
    $random
    2. Simulation control Tasks
    $reset
    $stop
    $finish
    3. Simulation time related Tasks
    $time
    $stime
    $realtime
    Compiler directives
    A compiler directive may be used to control the compilation of a Verilog description. The grave accent mark( ` )denotes a compiler directive.
    A directive is effective from the point at which it is declared to the point at which another directive overrides it, even across file boundaries.
    `define
    `include
    `timescale
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    Reference- verilog HDL : A Guide to Digital Design and Synthesis
    By Samir palnitkar

Комментарии • 17

  • @nasirkhan-zk8dm
    @nasirkhan-zk8dm 2 года назад +2

    superb good work. kindly please make video course on UVM too

    • @vlsipoint
      @vlsipoint  2 года назад +2

      Thanks Nasir! Surely will make videos on UVM. Stay connected ✌✌

  • @bhuwankaushik4919
    @bhuwankaushik4919 4 месяца назад +1

    Mam if we have two blocking statement like
    a=0;
    a=1;
    $display("a = ",a);
    $monitor("a= ",a);
    what will be the output mam?

    • @PhysicsNomad01
      @PhysicsNomad01 4 месяца назад

      display: a = 1
      monitor: a = 0
      monitor: a = 1

  • @riyazuddinmohammed3508
    @riyazuddinmohammed3508 2 года назад +1

    at 1:24 in 2nd point i think instead of $strobe there should be $write. correct me if i am wrong

  • @kingwon7995
    @kingwon7995 Год назад

    Hello Ma'am!!
    Please can you make a series on VHDL Language too!!

  • @ramazain2264
    @ramazain2264 Год назад

    Hello
    The telegram group link doesn’t work do can you send another one?

  • @JNECLatheshav
    @JNECLatheshav Год назад

    Tq mam❤

  • @akhilapp1135
    @akhilapp1135 5 месяцев назад

    Mam link has expired

  • @shaiksaleem2204
    @shaiksaleem2204 2 года назад

    The given telegram link has expired can u provide new link to ask some doubts in verilog

  • @amruthn3272
    @amruthn3272 2 года назад +1

    Telegram link is not working

    • @vlsipoint
      @vlsipoint  2 года назад +1

      t.me/joinchat/9q2ZFEfADY5lZWVl
      Use this link to join the group.

  • @ashokk763
    @ashokk763 9 месяцев назад

    Telegram link pls

  • @darsanraj4563
    @darsanraj4563 2 года назад

    Hi Didi...
    can u just go a bit slow in videos???
    Becaus it is quite difficult to catch your words and points which u r saying Didi.....

    • @kavitha4914
      @kavitha4914 Год назад +1

      Even I felt the same 😅.No sooner I preferred to go with 0.75 x speed

  • @durgabhavanibadiganti3413
    @durgabhavanibadiganti3413 2 года назад

    mam can u share all the ppts to me

  • @ganeshbagnal6524
    @ganeshbagnal6524 7 месяцев назад

    It was too fast. Could not understand clearly...