Massive thanks again to Tescan! I hope you enjoyed this video and maybe recommend it to your friends if you liked it. This was so much more work than expected :D
Very much enjoyed, thank you for doing this! 24 years ago, I worked at an optical storage array vendor back from 1995 through 1998,, and our latest primary logic chip was considered groundbreaking at 450nm, which we developed collaboratively with Symbios Logic (I was just a lowly QA engineer in my Sr year of high school).. After I left, the company eventually closed their doors in 2001 with their half of the rights to the chip technology sold to Symbios Logic, who at this point had been acquired by LSI Logic, which was eventually merged with Syntax and renamed to Engenio Information Technologies, who later spun off it and sold Engenio to NetApp back in 2011 for about $500M, who still makes and sells storage systems based on Symbios Logic technology as NetApp E-series nearly a quarter of a century later. It's crazy to realize that the storage logic controller technology we developed back in 1995 is still the foundation for Enterprise storage systems being produced today, and has probably been part of at least 1 trillion USD worth of storage systems sold over the past 25 years, and any of us that have ever used an LSI logic storage controller has run at least some of the storage IO logic that we developed so long ago. Also amazing is that I still find this stuff so interesting and exciting.
@PewPewZee LawL You're entirely right. I hope that he will create a mirror of this and his video channel with BitChute to make sure that he cannot be deplatformed by censorship from RUclips/Google or others.
@@der8auer For the record, I'd rather you just record one video in German, then just add subtitles. That way you're not having to interview people twice, and we get to see a more genuine conversation. Not a conversation repeated "for the cameras"
not really humility... he did the stupid thing to prove his own point. so it's more like condescension. which still doesn't detract from the excellence of the video :D
This reminds me of CSI. When they are like , "enhance that image" and proceed to read a licnese plate 30 miles away using a 2 megapixel security camera
no, that was like 6 pixels making up the entire license plate. Then they pulled a zoomed in HD image out of their butt. I'm like yeah........complete BS.
"Which is ok I guess..." The look says "I'm not angry. Just.. disappointed" 😂 Thank you for doing all this. I knew the different processes effectively measure different things, but it's nice to see the transistors in the flesh. Not having multi-thousand pieces of equipment in my house, it's nice to be given this opportunity through your work and the cooperation of the nice people at Tescan. Thank you all very much n
It's pretty much exactly what I expected. Gordon Ung said it ages ago; what TSMC is calling 7nm is basically what Intel are calling 10nm. The same as TSMC's 10nm was basically the same as Intel's 14nm. Or to put it another way, AMD CPUs aren't a 2 step smaller process than Intel, it's basically 1 step. That said, manufacturing at this scale still blows my mind. Very cool video Roman.
@@surtrgio Going off of transistor density, it's somewhere between the two. Samsung's 7nm process uses EUV lithography which limits production capacity and increases cost whereas their 8nm does not. I'm guessing Nvidia just went for the cheap route.
You kind of have to imagine the process as taking an image and drawing it onto the surface of the chip. Intel's images are lower resolution, but each transistor is fewer pixels. TSMC uses higher resolution but each transistor has more detail and more pixels in the source image.
@@markwei8108 That's really not an issue anymore at this time on Samsung's 7 nm node ..... In January it was still an issue so Nvidia couldn't really go with it but it's no longer a problem and IBM just made a large order for their new Power10 server CPUs on the 7 nm node ...... All the nonsense about there being a problem with Samsung 8 nm was pure bullsh*t and I suggest you stop listening to anyone who was spreading that bullsh*t because they have no credibility anymore ...... All Samsung phones have SoC's on that node since 1st Q 2019 and I've been making designs (Commercial HVAC and building control systems) around Samsung ARM SoC's off that node for almost 18 months Don't believe everything you hear on the Internet applies more today than it did even 25 years ago ......
In time we'll probably see some AMD branded strawberries on the AMD fan merchandise website lol. When he said Blueberry, I immediately thought of Charlie and the chocolate factory where one of the characters turns into a blueberry (well sort of ) haha. After all Intel did sort of turn into a blueberry with ice lake on laptops 😅.
likely will never happen.. that stuffs locked up tighter than Fort Knox and even if you some how managed to see how a semiconductor factory worked you'd never be able to speak about it.
@@sirmonkey1985 For 7nm stuff yeah they're super secretive. But foundries are pretty open about older processes. I'm pretty sure you can get some pretty amazing detail on 45nm for example.
If you did not see it at all, there are already videos of the process (sadly not in HD). This one ruclips.net/video/F2KcZGwntgg/видео.html shows all steps of wafer manufacturing and has nice explanation. Just keep in mind that most modern fabs are using larger 300mm wafers so everything has to be scaled up. And this one ruclips.net/video/AMgQ1-HdElM/видео.html shows CG animation of the process (makes it easier to see what is happening). If you search, there are much more videos.
Really cool analysis. One quick comment. Few years ago, TSMC naming scheme for its process started to reflect the smallest feature it can print on a wafer, which is a "fin" of a finfet transistor. Therefore if you measure width of a fin (3D structure orthogonal to the gate), it should come out closer to a "7nm" give or take 1 or 2 nm. - at least for the first generation 7nm. But of course this makes measurement under the electron microscope that much more challenging. Intel 14nm still adheres to a older naming scheme, but it is roughly equivalent to TSMC 10nm half node process. Thought the ++++ may have shrunk it down to closer to 9nm. Most importantly the characteristic of the transistor is quite different. Ex. TSMC 7nm transistor can operate at a lower voltage and requires a lower voltage to turn it "on" or "off" at the gate. Therefore its dynamic power dissipation tends to be lower than that of Intel's 14nm per unit area.
I think the Intel +++ is more about improvement in 3D fin structure for more frequency range, lower voltages, and higher yields rather than density improvement. I think they all know that now this is more of a marketing term that a physics. They know consumer cares about having smaller number so they give this.
@@NizarElZarif Improvements in process can even lead to increases in density, but not in performance per watt. That's how you see the so-called half-nodes, like Samsung's 8nm (Shrunk 10nm)
@@jonathanmitchell9779 The 14nm only stopped at +++, Rocket Lake will be made with the original 14nm node because the refinements did not make it overall better especially for desktop use
This was like watching surgery but on microscopic level. Very interesting and things only get even smaller soon 5nm and so on - mind blowing Thanks for the effort you put on this der8auer
This video gives me headache... I already watched electron microscope images, but this video is mind blowing. It's hard to comprehend how smalls current transistors are.
Thank you ! Driving home that the “nm” node of these companies are not comparable is really important - it has more to do with marketing and PR more than a technical rationale.
Even those 7n, 14n and so on numbers do not really matter, this video series does matter an immense lot. Thank you so much Roman and all the people worked for this piece, the trilogy provided the information probably no one put out before and it's very interesting, educational, and helpful! And thanks always bother to invest your time to make an English version of the videos!
Excellent. Not too many YT channels are capable of investigating these seemingly unknowable questions, given the scales involved. I feel like I've learned something after watching this.
This was an amazing way to show my son how a cpu looks and works. Reminded me about the tech shows i used to watch on BBC 2 in the early 80's Way more in depth explanations of what it's all about.
Great comment: "It's not that simple" Thank you for an incredible look at the insides of our current technology used in our phones and computers. Sure come a long way from the days when we could see the structures through the windows on EPROMS! I look forward to the next generation!
Thank scale makes a surgeon's steady hand look like a drunk person. (I have a surgeon who wants to run some wires down my spine (a Spinal Cord Stimulator/ SCS), I'm not keen on the idea).
True, but the pictures of what I have only read about was wery well worth of it! Maybe that strawberry version 4 vs Blueberry version 8 naming would be better for marketing ;)
Thank you der8auer for making this video. After seeing this,it makes me really think where we are now in this present century.. How far the technology has evolved in the last decades... Also,numbers are just "numbers". It's the performance which matters.
It's amazing how clear and and sharp these electron microscope images are. I had some experience with a ~1980s electron microscope and the micrographs always looked more like Rorschach's ink blots open to interpretation.
This was fascinating, thanks. It answered several questions I'd often wondered about. I wondered how they were getting around the problem quantum tunnelling at 7nm and now even 5nm but I see they're just not quite at the scale for it to be a problem in reality...
Intel and TMSC (and others) are buying the lithography machines to manufacture their architectures at the same company (ASML). To me it is logical that they should have about the same spatial definition.
Intels 10 nm is produced with the same 193 nm light (deep UV) as their 65 nm node was/is. How do you make features smaller than the wavelength of light? Self-aligned multipatterning and immersion lithography. TSMC used to use DUV for 7 nm but now use 13.5 nm EUV wavelength of light and features are approximately the same size as their old DUV 7 nm process. The wavelength of light is less relevant than you expect and improvements in lithography happens much faster than the improvement in light source.
@@soylentgreenb I think intel was planning to move to EUV on 7nm wth GAAFET transisitor but they are facing roadblocks and delays. TSMC has some part of the process EUV in N7, i think N7+ has even more EUV processes, but 5nm should be fully EUV but want FAAFET at 3 or 2nm.
It's just a lithography tool. it only does what the process engineers make it do. It's like saying your auntie's pie is as good as my grandma's because they use the same oven :) They have the same capability, but it doesn't make any silicon comparison possible.
nm designation is the 'smallest feature on the die' supposedly so... difference between 14 and 7nm is... one would think 1/2 as big so double the room to add stuff but in reality... no idea. Being a machinist for the last 10 years and knowing what 1 micron is and 100 microns are... this is some of the most fascinating stuff I've ever seen. Thank you so much, der8auer!!
Just starting the video, over the passed 10 years ive assumed the NM number was just a marketing term for the fab to convey generational improvements and that the actual number was close but not accurate.
Few years ago i've seen an article about it ,they said that intel 10nm is more dense then TSMC 7nm . At that time i tarted wondering if the numbers are just marketing stuff
Brilliant! thanks for the English too!. What amazes me even from 30yrs ago is how the chips were even manufactured especially the accuracy of 1000's of components involved in a mm. (billions now of course)
Really amazing work and pictures! Have you tried getting in contact with ASML or ZEISS for a little showcase of how these tiny structures even get produced? In my opinion the next logical step :D Thanks a lot for your amazing content!
Fascinating, I had no idea it is basically just marketing, we will take your sound advise and look at the benchmarks. Thank you for all the work and effort, it is appreciated by many.
Thanks a lot man! That was super useful. Did you know the answer to your question before your discussion with the AMD engineer? I for one genuinely thought that 7nm amd could be compared with 14nm Intel- not half the size, but still comparable. Now we know why thats wrong. Thanks again!
To me statement that processor was made in 7nm or 14nm lithography means that smallest transistors in such product will be that size but there can be bigger ones. Generally with the smaller lithography the average transistor count per area should increase. Let's see how wrong I am... Edit: Well, my second sentence was quite correct...
the 14,10 nm should refer to the gate size, not the transistor size. At least in the old process. Nowadays, they are more marketing terms than actual sizes. Samsung is probably the worst in this regard, where 14nm is basically a FinFet of a version of their 20nm with no improvement to density (but huge improvement to power efficiency and frequency because of FinFets). their new 8nm used by Nvidia is an Nvidia optimized version of their 10nm.
Extremely interesting. Shows very clearly how much marketing plays into all of this. The bottom line is exactly what you said in this video: observed macro performance is the only metric of consequence.
Delayed the video so you could send the info to both companies in hopes of getting some more information, and making sure you are relaying correct information to your fans. What a great way to go about it. Thanks you for the time and effort that you spent on this, and thank you for helping everyone learn more about something like this, that consumers typically have no way of learning from a third-party entity that doesn't sell these items.
Before the video, it's been my impression that intel's process is smaller per nm than TSMC's. If I had to take a guess, I'd say that if we were to put 14nm Intel on the TSMC scale, it'd be around 10nm.
@@Megalomaniakaal well the 14nm density hasn't increased with a +, it actually was just better frequency/voltage curves and ++ actually loosened the density a bit. TSMC doesn't use a + unless its a density and power improvement, like N7+ and N5+ both have around 10-15% density improvements and power or performance improvements. Samsung does have their 8nm and 10nm that are similar, and I'm not sure what the improvements between those are.
"So, here we have a piece of silicone about as long as the third of a human hair's width. Let's shave some off the edge, and glue it somewhere. Then zoom into it a couple thousand times while shining an electron beam through it." JFC, that hurts my brain it's so small.
"Hey Intel care to comment on why your competitor uses a metric that makes it seem like their products are twice as good as yours, while in reality you 2 are closer than everyone thinks?" intel: ..................... ... I guess Intel is still sleeping on the job ...
Actually Intel was not closer, and that was the problem. If Intel could compete with TSMC manufacturing process, they would also pack 16 cores on a desktop CPU - something that they could not do obviously.
@@bouxesas2046 "I too am not an industry expert but make claims about industry problems" (Putting 16 cores on a package is more difficult than just the node size)
Bouxesas it’s not that simple. AMD combines multiple ‘chiplets’, each with several cores, to make a 16 core cpu. Intel has a monolithic design where all the cores are on one piece of silicon. While AMD’s approach gives higher yields, it introduces latency because chiplets now have to communicate across a greater distance than if the cores were all on one die. Also, don’t forget that intel DOES have >16 core cpus, they’re just marked as Extreme or Xeon SKUs
TSMC is not Intel's competitor. If TMSC call their process node 7nm, what should AMD do? edit: I stand corrected, they technically are. My bad, I thought you were talking about AMD. My point about AMD still stands tho'.
i know this content isnt the kind that gets you the most views. but i think this is amazing. Keep doing this kind of work. i love the science of how it works. gives me a great understanding of the product Danke
From what I can tell of a node's name, a halving of the node size corresponds approximately to a doubling of density (half the area) alongside an improvement in efficiency of roughly 50% (half the power). On a planar scale halving your measurements quadruples your density and as silicon is still basically a single layer of logic, the 3D construction of finfet still operates within planar densities. X2 density 1/2 power results in x4 scaling and thus a full node which is approximately half size half power or 1/4 and basically a quick and dirty reference. There's a method to naming nodes, it's just not consistent between manufacturers and will become silly when we hit the first picometre named node.
14 and 7 transistor nanometers are like 20 centimeter fans: you'd think the number would mean something, but everyone makes whatever the hell they want.
I think they're marketing buzzwords that both companies have allowed to be accepted because it lets them *both* pretend like they're making more advancements than they are. Now let's watch and see if I'm right.
Studying and working with material in nanoscale is mindblowing. As a material chemist, i know how hard and fascinating it is. Honestly, i'm a bit dissapointed that the conclusion was "it's not the size, but just the process". Anyway, good video, love combining something that i like with something that i do everyday.
Thanks for that explanations. Answering the simple question if it's better to have lesser number of nm, it depends because it doesn't exactly mean that the transistor are smaller. But answering the question if it's better to have smaller transistors, then yes, it's better (from Power consumption point of view, hence tdp, etc). Also transistor itself has it's capacity and it always matters when it comes to speed(frequencies). Correct me if i'm wrong
I used to use the original FIB developed at Ronler Acers Intel Campus in Hillsboro, OR. Later FEI involved and continued development. Thanks for the look at the latest equipments.
Thank you Derbauer that was something I will cherish its always facinated me how they pack the transistors in chip not many tech channels show the inner workings.
I think basically it is either the total area of some gate/ by no of transistors. And then the length which will give channel length of one transistor. That is what is called as 14nm, 7 nm, Channel Length. Initial Thoughts
Fascinating, I will have to rewatch the whole thing, because distracted as I am now, I understood little of the actual imaging stuff. The available tools are absolutely mindboggling and I am sure some scientists would have been willing to sell their firstborn children for something like this 50 years ago.
finally! this is the video we need to sew them in court! if they cant prove the advertised size then we need to be compensated by money! time to get in contact with the lawyers!
I love this kind of stuff! Excellent work showing the deep technical detail in these chips in such a way as to give us a physical reference for how incredibly complex and small these wonders of modern technology are.
Very cool! I was entranced just watching the process of this, and trying to wrap my head around the incredible size scale. Especially when the needle was being attached.
I love the Seasonic stinger at the beginning of the video. It's got that 2 seconds to queue me up and then I yell over the announcer, in my best monster truck/wwf voice. I totally kill his delivery.
I've been working for electron microscopes producer for almost 3 years... (FEI co. before, Thermofisher Scientific now) - it's awesome technology. Great video that explanins a lot about it.
Working in the industry back in the midst 2000's I can only imagine the stress of trying g to fit to these standards now. Just damn. I works and fixed and cleaned the ecto machines that made the chips on the wafers. Also later working on building the full silicone crystals....I can only imagine how strick it is now. Just wow. How much we have achieved in such a small time.
Very nice information. I always thought this measure was about the thickness of the lanes conecting the transistor. And I remember someone talking about a limit of 4 nm that could not be broken because electrons may simply jump from one lane to another.
![Intel - From Inventors of the CPU to Laughing Stock [Part 2]](http://i.ytimg.com/vi/LoTx9LQIKEA/mqdefault.jpg)
Massive thanks again to Tescan! I hope you enjoyed this video and maybe recommend it to your friends if you liked it. This was so much more work than expected :D
Massive thanks for these videos, too. Good stuff.
After watching this, I came away feeling that in a few years time, @Der8auer will be modding the chip die's.
Very much enjoyed, thank you for doing this! 24 years ago, I worked at an optical storage array vendor back from 1995 through 1998,, and our latest primary logic chip was considered groundbreaking at 450nm, which we developed collaboratively with Symbios Logic (I was just a lowly QA engineer in my Sr year of high school).. After I left, the company eventually closed their doors in 2001 with their half of the rights to the chip technology sold to Symbios Logic, who at this point had been acquired by LSI Logic, which was eventually merged with Syntax and renamed to Engenio Information Technologies, who later spun off it and sold Engenio to NetApp back in 2011 for about $500M, who still makes and sells storage systems based on Symbios Logic technology as NetApp E-series nearly a quarter of a century later. It's crazy to realize that the storage logic controller technology we developed back in 1995 is still the foundation for Enterprise storage systems being produced today, and has probably been part of at least 1 trillion USD worth of storage systems sold over the past 25 years, and any of us that have ever used an LSI logic storage controller has run at least some of the storage IO logic that we developed so long ago. Also amazing is that I still find this stuff so interesting and exciting.
Roman,my cousin. Your channel is too good.
Would love to see a GAAFET video! Thanks for the great content
This is some internet gold.
thanks :)
Thanks Roman. Very insightful. Something AMD and Intel marketing don't want you to know.
It is internet platinum!
This was truly some internet gold about nanometers scaling. Wow. Very instructive video.
@PewPewZee LawL You're entirely right. I hope that he will create a mirror of this and his video channel with BitChute to make sure that he cannot be deplatformed by censorship from RUclips/Google or others.
Thank you for doing this video in English and German. I know it's a lot of work but thank you once again.
thanks :)
Definately thanks. I watched the bathtub water-cooling video in German. Didn't understand a word, understood everything.
thanks!!!!
@@der8auer For the record, I'd rather you just record one video in German, then just add subtitles. That way you're not having to interview people twice, and we get to see a more genuine conversation. Not a conversation repeated "for the cameras"
I once thought der8auer used some sort of super-magical auto video translation thing before realizing he really done two videos everytime.
“It’s as stupid as what we just did”.
Insight and humility which do not detract from this excellent video. Thanks bud! Nice one
not really humility... he did the stupid thing to prove his own point. so it's more like condescension. which still doesn't detract from the excellence of the video :D
agree to disagree
This reminds me of CSI. When they are like , "enhance that image" and proceed to read a licnese plate 30 miles away using a 2 megapixel security camera
I don't why I read that as "kuzzy", like SCSI without the the S.
@Aaron Morrow I don't think AI processing would be the right choice of a tool when solving crimes based on pictures as evidence ^^
no, that was like 6 pixels making up the entire license plate. Then they pulled a zoomed in HD image out of their butt. I'm like yeah........complete BS.
When you think you just got bitten by a mosquito, in reality it is an electron microscope pointing at you.
Get me a hard copy right there.
"Which is ok I guess..."
The look says "I'm not angry. Just.. disappointed" 😂
Thank you for doing all this. I knew the different processes effectively measure different things, but it's nice to see the transistors in the flesh. Not having multi-thousand pieces of equipment in my house, it's nice to be given this opportunity through your work and the cooperation of the nice people at Tescan. Thank you all very much n
I had no expectations :D
@@der8auer it was nice of the AMD engineer to take the time to have a proper chat though :)
It's pretty much exactly what I expected. Gordon Ung said it ages ago; what TSMC is calling 7nm is basically what Intel are calling 10nm. The same as TSMC's 10nm was basically the same as Intel's 14nm. Or to put it another way, AMD CPUs aren't a 2 step smaller process than Intel, it's basically 1 step.
That said, manufacturing at this scale still blows my mind. Very cool video Roman.
It does make me then Wonder where Samsung's 8nm lies in between those two.
@@surtrgio Going off of transistor density, it's somewhere between the two. Samsung's 7nm process uses EUV lithography which limits production capacity and increases cost whereas their 8nm does not. I'm guessing Nvidia just went for the cheap route.
You kind of have to imagine the process as taking an image and drawing it onto the surface of the chip. Intel's images are lower resolution, but each transistor is fewer pixels. TSMC uses higher resolution but each transistor has more detail and more pixels in the source image.
Except TSMC's 7nm has been working quite well while Intel has been struggling with 10nm
@@markwei8108 That's really not an issue anymore at this time on Samsung's 7 nm node ..... In January it was still an issue so Nvidia couldn't really go with it but it's no longer a problem and IBM just made a large order for their new Power10 server CPUs on the 7 nm node ...... All the nonsense about there being a problem with Samsung 8 nm was pure bullsh*t and I suggest you stop listening to anyone who was spreading that bullsh*t because they have no credibility anymore ...... All Samsung phones have SoC's on that node since 1st Q 2019 and I've been making designs (Commercial HVAC and building control systems) around Samsung ARM SoC's off that node for almost 18 months
Don't believe everything you hear on the Internet applies more today than it did even 25 years ago ......
This is the best visualization of finfet I've seen and i can finally see it in my brain. Thank you!
It's amazing to see the platinum build up, and the silicon "melting".
I wonder how much platinum gas costs lol. Their byproduct and trash is literally gold lol.
Intel Blueberry
AMD Strawberry
These are the new CPUs
🤣🤣🤣🤣
In time we'll probably see some AMD branded strawberries on the AMD fan merchandise website lol. When he said Blueberry, I immediately thought of Charlie and the chocolate factory where one of the characters turns into a blueberry (well sort of ) haha. After all Intel did sort of turn into a blueberry with ice lake on laptops 😅.
Its better than Intel's current naming schema ;)
Well, this would make pretty neat merch!
That are actually great names imho xD
I want a Raspberry CPU then
Can you show us how a silicon wafer or ingot is grown next? I've always wanted to see the process.
likely will never happen.. that stuffs locked up tighter than Fort Knox and even if you some how managed to see how a semiconductor factory worked you'd never be able to speak about it.
ruclips.net/video/aWVywhzuHnQ/видео.html
@@sirmonkey1985 For 7nm stuff yeah they're super secretive. But foundries are pretty open about older processes. I'm pretty sure you can get some pretty amazing detail on 45nm for example.
ruclips.net/video/AMgQ1-HdElM/видео.html
If you did not see it at all, there are already videos of the process (sadly not in HD). This one ruclips.net/video/F2KcZGwntgg/видео.html shows all steps of wafer manufacturing and has nice explanation. Just keep in mind that most modern fabs are using larger 300mm wafers so everything has to be scaled up.
And this one ruclips.net/video/AMgQ1-HdElM/видео.html shows CG animation of the process (makes it easier to see what is happening). If you search, there are much more videos.
Really cool analysis. One quick comment. Few years ago, TSMC naming scheme for its process started to reflect the smallest feature it can print on a wafer, which is a "fin" of a finfet transistor. Therefore if you measure width of a fin (3D structure orthogonal to the gate), it should come out closer to a "7nm" give or take 1 or 2 nm. - at least for the first generation 7nm. But of course this makes measurement under the electron microscope that much more challenging.
Intel 14nm still adheres to a older naming scheme, but it is roughly equivalent to TSMC 10nm half node process. Thought the ++++ may have shrunk it down to closer to 9nm.
Most importantly the characteristic of the transistor is quite different. Ex. TSMC 7nm transistor can operate at a lower voltage and requires a lower voltage to turn it "on" or "off" at the gate. Therefore its dynamic power dissipation tends to be lower than that of Intel's 14nm per unit area.
I think the Intel +++ is more about improvement in 3D fin structure for more frequency range, lower voltages, and higher yields rather than density improvement. I think they all know that now this is more of a marketing term that a physics. They know consumer cares about having smaller number so they give this.
As far as I understand the 7nm should refer to the extension of the gate between the source and drain connections on the fin.
Intel 14nm++++++++++++++(/s) fins are also roughly ~7nm, IIRC
@@NizarElZarif Improvements in process can even lead to increases in density, but not in performance per watt. That's how you see the so-called half-nodes, like Samsung's 8nm (Shrunk 10nm)
@@jonathanmitchell9779 The 14nm only stopped at +++, Rocket Lake will be made with the original 14nm node because the refinements did not make it overall better especially for desktop use
The worth of this video [series] cannot be overstated. Thank you for this series, Roman.
This was like watching surgery but on microscopic level. Very interesting and things only get even smaller soon 5nm and so on - mind blowing
Thanks for the effort you put on this der8auer
This video gives me headache... I already watched electron microscope images, but this video is mind blowing.
It's hard to comprehend how smalls current transistors are.
I agree. 100 million transistors per square millimeter is insane!
7nm is about 20 silicon ATOMS. Crazy to think there are billions of transistors in a modern chip
I do Transmission Electron Microscopy as my work but this is on another level. And STEM is amazing I wish I can use that some day.
This was the coolest and most informative CPU video I have ever seen.
Thank you ! Driving home that the “nm” node of these companies are not comparable is really important - it has more to do with marketing and PR more than a technical rationale.
Sometimes the RUclips algorithm does its job. I'm so happy to have found this video.
Please don't say that or Google will change it to make it not work!
14:32 the cat doesn't seem to be amused with the marketing vs. actual sizes :)
It's my cousin ginger cat 😼🤭
14:55 Cat is not in a focus. Literally unwatchable.
Meow 😼
Agree! We need more focus on that good looking orange cat.
THAT CAT IS SO CUTE
Even those 7n, 14n and so on numbers do not really matter, this video series does matter an immense lot. Thank you so much Roman and all the people worked for this piece, the trilogy provided the information probably no one put out before and it's very interesting, educational, and helpful! And thanks always bother to invest your time to make an English version of the videos!
This is one of the most interesting videos I've ever watched.
Excellent. Not too many YT channels are capable of investigating these seemingly unknowable questions, given the scales involved. I feel like I've learned something after watching this.
This was an amazing way to show my son how a cpu looks and works.
Reminded me about the tech shows i used to watch on BBC 2 in the early 80's
Way more in depth explanations of what it's all about.
Computer CHronicles perhaps?
@@ToTheGAMES Not sure but it was always on around 10am and had a segment for school's that we all watched as school children in class in 85
BBC 👍🏿👍🏿👍🏿
@@ToTheGAMES NNN on ok on
I've been looking for video that can show how transister looks like... Finally found this GOLD channel.
Great comment: "It's not that simple"
Thank you for an incredible look at the insides of our current technology used in our phones and computers. Sure come a long way from the days when we could see the structures through the windows on EPROMS! I look forward to the next generation!
You just take tech and hardware to another dimension of knowledge. Things you are not able to learn anywhere else on YT. Thanks for doing this.
thank you :)
Tescan SEMs are awesome, some of the best I've ever used.
Der8aeur : if you can cut that 7nm transistor to me that would be great.
Operator : pilot_sweating_meme.png
Thank scale makes a surgeon's steady hand look like a drunk person.
(I have a surgeon who wants to run some wires down my spine (a Spinal Cord Stimulator/ SCS), I'm not keen on the idea).
This kept me glued to the screen like a kid. Amazing content Roman!
der8auer just destroyed some other marketing mith. Danke!
This was a well known thing even before. He's just sharing the info so more will find out about it.
True, but the pictures of what I have only read about was wery well worth of it!
Maybe that strawberry version 4 vs Blueberry version 8 naming would be better for marketing ;)
Thank you der8auer for making this video.
After seeing this,it makes me really think where we are now in this present century..
How far the technology has evolved in the last decades...
Also,numbers are just "numbers". It's the performance which matters.
It's amazing how clear and and sharp these electron microscope images are. I had some experience with a ~1980s electron microscope and the micrographs always looked more like Rorschach's ink blots open to interpretation.
This was fascinating, thanks. It answered several questions I'd often wondered about.
I wondered how they were getting around the problem quantum tunnelling at 7nm and now even 5nm but I see they're just not quite at the scale for it to be a problem in reality...
Perfect ! This is how youtube and tech channel should be. I have enough of stupid joke script, and repeated news.
Intel and TMSC (and others) are buying the lithography machines to manufacture their architectures at the same company (ASML). To me it is logical that they should have about the same spatial definition.
Intels 10 nm is produced with the same 193 nm light (deep UV) as their 65 nm node was/is. How do you make features smaller than the wavelength of light? Self-aligned multipatterning and immersion lithography.
TSMC used to use DUV for 7 nm but now use 13.5 nm EUV wavelength of light and features are approximately the same size as their old DUV 7 nm process. The wavelength of light is less relevant than you expect and improvements in lithography happens much faster than the improvement in light source.
@@soylentgreenb I think intel was planning to move to EUV on 7nm wth GAAFET transisitor but they are facing roadblocks and delays. TSMC has some part of the process EUV in N7, i think N7+ has even more EUV processes, but 5nm should be fully EUV but want FAAFET at 3 or 2nm.
It's just a lithography tool. it only does what the process engineers make it do. It's like saying your auntie's pie is as good as my grandma's because they use the same oven :)
They have the same capability, but it doesn't make any silicon comparison possible.
Le Doynier overlay is the key driver of yield and leakage
Wow Tescan are absolute legends for letting you use there machines. The videos were fantastic as well Der8auer.
thanks!
18:29 AMD THREADRIRRRRR
nm designation is the 'smallest feature on the die' supposedly so... difference between 14 and 7nm is... one would think 1/2 as big so double the room to add stuff but in reality... no idea.
Being a machinist for the last 10 years and knowing what 1 micron is and 100 microns are... this is some of the most fascinating stuff I've ever seen. Thank you so much, der8auer!!
Just starting the video, over the passed 10 years ive assumed the NM number was just a marketing term for the fab to convey generational improvements and that the actual number was close but not accurate.
Few years ago i've seen an article about it ,they said that intel 10nm is more dense then TSMC 7nm . At that time i tarted wondering if the numbers are just marketing stuff
I mean you weren't too far off!
@@mehdidamfs3112 Wait, it's all marketing?
Always has been.
Your right, because Intel has had some 8nm gates since Haswell. But continued to name it 14nm based on the majority of the gates
@@Azraleee i know it marketing , but i didn't know that the naming is purely marketing , i thought it is based on real lithography numbers
Brilliant! thanks for the English too!. What amazes me even from 30yrs ago is how the chips were even manufactured especially the accuracy of 1000's of components involved in a mm. (billions now of course)
Nice work Roman, and nice of Amd to have an engineer contact you etc.
No man on earth can explain like this you're the real derbauer 🎉 and this is gonna be another feather in your cap
Really amazing work and pictures!
Have you tried getting in contact with ASML or ZEISS for a little showcase of how these tiny structures even get produced?
In my opinion the next logical step :D
Thanks a lot for your amazing content!
Yes, ASML is almost close to German as well. Would be awesome.
That would be nice, although maybe impossible.
@@diavalus why? ASML would benefit from showing off and talking about their technology
Fascinating, I had no idea it is basically just marketing, we will take your sound advise and look at the benchmarks. Thank you for all the work and effort, it is appreciated by many.
I'm sticking with AMD strawberries.
Meh i have 1000+ strawberry plants ill go with intel fruit.
Yeah that sounds like a plan.
@Bruce Wang nope team cyan or team yellow are better than team red
Which is worse, strawberry allergy or blueberry allergy? 😎
Almost completing the IC designing module using Pyxis, to see the actual transistor and not just in CAD is a real eye-opener! Thanks.
"Just look at benchmarks" That gets a like from me!
I have enjoyed just how many new nano leaf looking panels you have grown on the wall behind you
Thanks a lot man! That was super useful. Did you know the answer to your question before your discussion with the AMD engineer? I for one genuinely thought that 7nm amd could be compared with 14nm Intel- not half the size, but still comparable. Now we know why thats wrong. Thanks again!
I had no idea hook how long and detailed this process is. Thank you and the lab for doing this. Truly fascinating.
To me statement that processor was made in 7nm or 14nm lithography means that smallest transistors in such product will be that size but there can be bigger ones. Generally with the smaller lithography the average transistor count per area should increase. Let's see how wrong I am...
Edit: Well, my second sentence was quite correct...
the 14,10 nm should refer to the gate size, not the transistor size. At least in the old process. Nowadays, they are more marketing terms than actual sizes. Samsung is probably the worst in this regard, where 14nm is basically a FinFet of a version of their 20nm with no improvement to density (but huge improvement to power efficiency and frequency because of FinFets). their new 8nm used by Nvidia is an Nvidia optimized version of their 10nm.
The only tech channel I trust. This guy is so smart and really knows his stuff
One of the coolest videos I've seen. So cool, so informative.
Extremely interesting. Shows very clearly how much marketing plays into all of this. The bottom line is exactly what you said in this video: observed macro performance is the only metric of consequence.
Have been waiting for this, thank you
Delayed the video so you could send the info to both companies in hopes of getting some more information, and making sure you are relaying correct information to your fans. What a great way to go about it. Thanks you for the time and effort that you spent on this, and thank you for helping everyone learn more about something like this, that consumers typically have no way of learning from a third-party entity that doesn't sell these items.
thanks man!
Performance per watt is the only metric that matters, well when comparing closely matched products.
Great job! Very nice demonstration that transistor node names do not represent a physical dimension, beginning in around 1997.
Before the video, it's been my impression that intel's process is smaller per nm than TSMC's. If I had to take a guess, I'd say that if we were to put 14nm Intel on the TSMC scale, it'd be around 10nm.
Well you got me stumped, I really did believe that 7nm stuff was half the size of 14nm. Thanks for teaching me a new thing, really interesting.
So intel or amd or any foundry for that matter could "move" to a smaller node just by making optimizations to the existing one and changing the name
Yeah intel could have reasonably have named the 14+++++ 10 instead. But they didn't want to.
@@Megalomaniakaal well the 14nm density hasn't increased with a +, it actually was just better frequency/voltage curves and ++ actually loosened the density a bit.
TSMC doesn't use a + unless its a density and power improvement, like N7+ and N5+ both have around 10-15% density improvements and power or performance improvements.
Samsung does have their 8nm and 10nm that are similar, and I'm not sure what the improvements between those are.
The closer the gate the more efficient it becomes for electricity to pass through faster , thanks for the info
Not all transistors in a CPU are the same size, so how do you know that you got the smallest transistors?
This is the best observation for the video! Good catch.
He does specify later that he asked an AMD engineer if he got the right data and it was confirmed.
"So, here we have a piece of silicone about as long as the third of a human hair's width. Let's shave some off the edge, and glue it somewhere. Then zoom into it a couple thousand times while shining an electron beam through it."
JFC, that hurts my brain it's so small.
So happy your cat is in video and quite well now
nm became a meaningless marketing term. It would be difficult to educate end-consumers about a given process's characteristics.
its a bit like only talking about horse powers and not about torque
Blast processing
This is so cool. Seeing the footage of the actual cutting of the chip and preparation of the samples. Thank you for going into such a detail!
Intels reaction: Images from our cpu tech -> lawyer comes to your office xd
This is absolutely insane! I can’t believe how much precision is involved in this.
"Hey Intel care to comment on why your competitor uses a metric that makes it seem like their products are twice as good as yours, while in reality you 2 are closer than everyone thinks?"
intel: .....................
... I guess Intel is still sleeping on the job ...
Actually Intel was not closer, and that was the problem. If Intel could compete with TSMC manufacturing process, they would also pack 16 cores on a desktop CPU - something that they could not do obviously.
@@bouxesas2046 "I too am not an industry expert but make claims about industry problems" (Putting 16 cores on a package is more difficult than just the node size)
There has never been a standard to measuring "nm" across Fabs, it's more marketing than anything. Intel can name their process whatever they want.
Bouxesas it’s not that simple. AMD combines multiple ‘chiplets’, each with several cores, to make a 16 core cpu. Intel has a monolithic design where all the cores are on one piece of silicon. While AMD’s approach gives higher yields, it introduces latency because chiplets now have to communicate across a greater distance than if the cores were all on one die.
Also, don’t forget that intel DOES have >16 core cpus, they’re just marked as Extreme or Xeon SKUs
TSMC is not Intel's competitor. If TMSC call their process node 7nm, what should AMD do?
edit: I stand corrected, they technically are. My bad, I thought you were talking about AMD. My point about AMD still stands tho'.
i know this content isnt the kind that gets you the most views. but i think this is amazing. Keep doing this kind of work. i love the science of how it works. gives me a great understanding of the product
Danke
thanks! Yes I agree it's not the massive views clickbait stuff but the content which means the most to me
I love the AMD Strawberry process, as opposed to Intel Blueberry+++.
From what I can tell of a node's name, a halving of the node size corresponds approximately to a doubling of density (half the area) alongside an improvement in efficiency of roughly 50% (half the power). On a planar scale halving your measurements quadruples your density and as silicon is still basically a single layer of logic, the 3D construction of finfet still operates within planar densities. X2 density 1/2 power results in x4 scaling and thus a full node which is approximately half size half power or 1/4 and basically a quick and dirty reference.
There's a method to naming nodes, it's just not consistent between manufacturers and will become silly when we hit the first picometre named node.
14 and 7 transistor nanometers are like 20 centimeter fans: you'd think the number would mean something, but everyone makes whatever the hell they want.
the precision of all these tools is quite remarkable.
Today I learned:
"nm" stands for "nonsensical metric"
Thanks for making these videos. This is seriously mind blowing stuff. Amazing how these engineers manage create these architectures.
I think they're marketing buzzwords that both companies have allowed to be accepted because it lets them *both* pretend like they're making more advancements than they are. Now let's watch and see if I'm right.
Fuck'n nailed it.
Studying and working with material in nanoscale is mindblowing. As a material chemist, i know how hard and fascinating it is.
Honestly, i'm a bit dissapointed that the conclusion was "it's not the size, but just the process".
Anyway, good video, love combining something that i like with something that i do everyday.
7/14 nm means nothing, just marketing fluff :)
Thanks for that explanations. Answering the simple question if it's better to have lesser number of nm, it depends because it doesn't exactly mean that the transistor are smaller. But answering the question if it's better to have smaller transistors, then yes, it's better (from Power consumption point of view, hence tdp, etc). Also transistor itself has it's capacity and it always matters when it comes to speed(frequencies). Correct me if i'm wrong
I used to use the original FIB developed at Ronler Acers Intel Campus in Hillsboro, OR. Later FEI involved and continued development. Thanks for the look at the latest equipments.
Thank you Derbauer that was something I will cherish its always facinated me how they pack the transistors in chip not many tech channels show the inner workings.
watching that process was more exciting than 3rd base... how does this guy not have millions of subs!
I think basically it is either the total area of some gate/ by no of transistors. And then the length which will give channel length of one transistor. That is what is called as 14nm, 7 nm, Channel Length. Initial Thoughts
Fascinating, I will have to rewatch the whole thing, because distracted as I am now, I understood little of the actual imaging stuff. The available tools are absolutely mindboggling and I am sure some scientists would have been willing to sell their firstborn children for something like this 50 years ago.
That machine and camera was insane!
HELLO WELKUM BACK TO NEW VIDEO!!!!
jeez okay roman thank you for blasting my eardrums with your infectious enthusiasm
This content is absolutely unique. Not sure what we did to deserve you!
It's the effective channel length between the source and drain terminals of a MOSFET DEVICE.
finally! this is the video we need to sew them in court! if they cant prove the advertised size then we need to be compensated by money! time to get in contact with the lawyers!
I love this kind of stuff! Excellent work showing the deep technical detail in these chips in such a way as to give us a physical reference for how incredibly complex and small these wonders of modern technology are.
Very cool! I was entranced just watching the process of this, and trying to wrap my head around the incredible size scale. Especially when the needle was being attached.
I love the Seasonic stinger at the beginning of the video. It's got that 2 seconds to queue me up and then I yell over the announcer, in my best monster truck/wwf voice. I totally kill his delivery.
I've been working for electron microscopes producer for almost 3 years... (FEI co. before, Thermofisher Scientific now) - it's awesome technology. Great video that explanins a lot about it.
Working in the industry back in the midst 2000's I can only imagine the stress of trying g to fit to these standards now. Just damn. I works and fixed and cleaned the ecto machines that made the chips on the wafers. Also later working on building the full silicone crystals....I can only imagine how strick it is now. Just wow. How much we have achieved in such a small time.
Very nice information. I always thought this measure was about the thickness of the lanes conecting the transistor. And I remember someone talking about a limit of 4 nm that could not be broken because electrons may simply jump from one lane to another.
This must be an expensive video, but it worth it!