U3L2.5 | JK FLIP FLOP | working of JK flip flop | JK Flip Flop Using NAND gate

#flipflops# digital logic design
J K flip flop resolve the undefined next state of SR FF when both was 1(S=R=1)
link for race around condition in JK flip flop
• U3L2.7 | Race around c...
previous year paper solution
KEC 302
2020-21
SECTION B
QUESTION 2(d)

[@Pihu_creation76]

Mam your explanation are superb ,No other person understands this way. best RUclips video mam ,I understood easily mam😊😊👍👍👍❤

[@TechnoTutorials2783]

Thanks dear
Keep watching

[@laibahameed4212]

Mam,your explanation and your way of teaching is very Adorable 🥰🥰😍,I always prefer your videos on RUclips,to move my step forward for exams,I had subscribed already your channel,but now,I m gonna recommend it to my friends also😍😍

[@TechnoTutorials2783]

Thank you dear for such a valuable feedback.
Once again thanku for your support

[@B.techPsitWallah]

Mam apki all video are fully explained and very easy method to explaination and helpful for aktu exam

[@TechnoTutorials2783]

Thank you

[@B.techPsitWallah]

Thank you mam

[@laibahameed4212]

Hello Mam,have you upload any video on D flip flop

[@TechnoTutorials2783]

ruclips.net/video/BIpHmcGr1Nk/видео.html

[@laibahameed4212]

Mam,clock k up and down arrows Kiya show kar rahy Hain

[@TechnoTutorials2783]

Up arrow means positive edge trigger means device will be on when clock goes 0 to 1
Down arrow just apposite of it