U3L2.4 | D Flip Flop | delay flip flop | Transparent Flip Flop | WORKING OF D FLIP FLOP

#D flip flop# statetable#delayFF
introduction of D Flip Flop
D Flip Flop using NAND Gate
State Diagram of D Flip Flop
truth table of D flip flop
State Table of D Flip Flop

[@Pushpam1995]

Best explanation of D-Flipflip

[@B.techPsitWallah]

Thank you mam

[@sarveshsingh6135]

🙏🙏🙏

[@Buthkun]

Mam for nor hm us gate ko pahle solve karte hain jiska input 1 hai and nand me us gate ko pahle solve karte hain jiska input 0 am i right

[@TechnoTutorials2783]

Yes

[@keshavsharma7415]

maam apne sr ki tt galat banai h

[@keshavsharma7415]

if posible reply early i have exam at 2

[@TechnoTutorials2783]

Jo sr ki hai wo only for.latch hai means starting two crossed nand
Agar hum input wale bhi include kare tab
sr =00 par no change meand Qn
Sr=01 par 0
SR=10 par 1
SR=11 PAR UNDEFINED
ruclips.net/video/B687Y_Cpu4s/видео.html
THIS LINK FOR D flip flop with wave form
Good luck for ur exam