ALU Design in Verilog with Testbench | Simulation in Modelsim | Arithmetic Logic Unit

This video provides you details about how can we design an Arithmetic Logic Unit (ALU) using Behavioral Level Modeling in ModelSim. The Verilog Code and TestBench for ALU are explained in this video.
Contents of the Video:
1. Arithmetic Logic Unit (ALU) Design
2. ALU Design using Behavioral Level Modeling in Verilog
2. ALU Design and Simulation in ModelSim
3. TestBench Code for ALU.
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[@balajiprithviraj5145]

Sir one doubt, in the test bench code you have given A=3'b0011 which not correct na? You have to give A=4'b0011 right? But still the code worked properly?

[@the_story_teller_india]

Can you please provide the verilog code for 8 bit ALU with logic, arithmetic and shifter unit

[@ajitantil1317]

for performing all these operation 8 bit alu will not be sufficient as it can only perform 8 operations and considering 4 arithmetic and 4 basic logic operation , you will have no slot left for performing shifting operations.
you can go for 16 bit alu for your project work.

[@udakasarinda3873]

I am working in a project, in which I use FPGA for simulation acceleration. There I need some help with hdl coding for FPGA and Nios II processer

[@royalekingdavid-clashroyal9088]

how is everything going to be in typed in English but you're speaking in a different language :/

[@AdityaRaj-cx9iu]

He is speaking in Hindi which is spoken in india. He is typing in English but for the better understanding,he used to speak in Hindi.