Full Adder Design using Gate Level Modeling in ModelSim | Verilog Tutorials

[@linda_erose]

Best verilog coding explained

[@aountariq9450]

Very good teacher really impressed

[@ElectroDeCODE]

Thanks

[@jimmi_jimmi]

Congrats on your great video. Is there any way to run gate level simulation?

[@shraddhakatara7131]

i have nothing in my workmodule what to do now

[@muskaanhayat980]

very nice explained thanx a lot

[@ElectroDeCODE]

Thanks

[@taioantv3050]

Verry good

[@WonderVerseX505]

really really impressive

[@ElectroDeCODE]

Thanks indeed

[@sohailabbasnageri3659]

thanks you bro

[@sarveshsingh6135]

Thank you

[@sattarsultan9799]

Thank You.

[@woldecosgrove]

can u speak English

[@ElectroDeCODE]

We are in a process of creating a new Playlist in English Language. Stay tuned

[@zahidi-rt3jn]

Thank you sir G