In my opinion at 23:30 , fork-join would be a better option to execute if conditions for both Head and Tail pointers simultaneously. Otherwise the compiler might execute the first if-else block first and then the second if-else block.
rd_ptr and wr_ptr shouldn’t be of 6 bits to count till 64, with this example max value of rd_ptr and wr_ptr can go up to 16. Please correct me if I am mistaken here.
buf_full signal should be asserted when the fifo_counter is 63, not 64 because it counts from 0. Therefore the statement should be corrected as "buf_full = (fifo_counter == 63);"
In the Verilog code the pointers are declared as: reg [3:0] rd_ptr, wr_ptr; shouldn't they be declared as: reg [5:0] rd_ptr, wr_ptr; So when they reach 63, then they are automatically set to zero when incremented again?
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In my opinion at 23:30 , fork-join would be a better option to execute if conditions for both Head and Tail pointers simultaneously. Otherwise the compiler might execute the first if-else block first and then the second if-else block.
rd_ptr and wr_ptr shouldn’t be of 6 bits to count till 64, with this example max value of rd_ptr and wr_ptr can go up to 16. Please correct me if I am mistaken here.
whom you are explaining 😂
buf_full signal should be asserted when the fifo_counter is 63, not 64 because it counts from 0. Therefore the statement should be corrected as "buf_full = (fifo_counter == 63);"
The counter is initialized as 0, so it is counting from 1, so it is correct.
No bro it has to be corrected to 63 , there initialized as 0 but after coming to 0 only it starts the count so it needs to get corrected
From 0 to 1 it counts 1 1 to 2 it counts 2 and 63 to 64 it counts 64 hence at 64th count it will be full
simple and clear explanation , extremely helpful
In the Verilog code the pointers are declared as:
reg [3:0] rd_ptr, wr_ptr;
shouldn't they be declared as:
reg [5:0] rd_ptr, wr_ptr;
So when they reach 63, then they are automatically set to zero when incremented again?
its actually reg [5:0] cos 64 mem locations
@@abhishekshankar1136sir can you plz give the test bench for above fifo code
Can you share a tutorial on asynchronous FIFO counter?
in first always block,in senstivity list only input will define .how u define output in sensitivuty list??
Very simple but informative video.
can you pls share source code with testbench
sir can u share the code
sir can u share the code for different read and write clocks
Is this
Hdl code
Or VLSL
Clear explaination. Pretty helpful. Thank you very much. :)
Well explained.
Nice explanation
Nice explaination b
excellent video
Please add video for and code for asynchronous FIFO
his lecture are in udemy
What is the benefit of using circular buffer ??
You mean instead of using a shift register, for instance?