Asynchronous FIFO Verilog Easy Explanation

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FIFO is an approach for handling program work requests from queues or stacks so that the oldest request is handled first. In hardware, it is either an array of flops or
read/write memory that stores data from one clock domain and on request supplies the same data to other clock domains following FIFO logic. An improved technique for FIFO design is
to perform asynchronous comparisons between the FIFO write and read pointers that are generated in clock domains and asynchronous to each other. The asynchronous FIFO pointer
comparison technique uses fewer synchronization flip-flops to build the FIFO. This method requires additional techniques to correctly synthesize and analyse the design, which are detailed in this paper. To increase the speed of the FIFO, this design uses combined binary/Gray counters that take advantage of the built-in binary ripple carry logic.
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