Cadence Layout View and Common Centroid - ECE x321 EDA Tutorial 3

In this video, we will switch to layout design for Cadence Virtuoso. Schematics are only half of the completed circuit, since a physical layout is required before fabrication. We will look at how to layout NMOS transistors (single and common centroid), resistors, capacitors, and PMOS transistors.
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[@LRV-TECH]

I liked it.))))))) Many things understood intuitively

[@aaroncarman]

I’m glad you liked it! :)

[@usefulknowledge6074]

1. You can press "k" to get the ruler.
2. The reason why the resistance did not go down after increasing the width is because the did not increase the width of the metal 1 of the via. If you want to reduce the resistance, you need to create more lanes for current to flow.

[@qemmm11]

Thanks 😊

[@chaoweiliu8343]

Thank you very much!

[@aaroncarman]

You're welcome! I am glad you enjoyed it :)

[@belkhiriahend698]

Hey! Your video is great, but I can't seem to find the library you used (ncsu techLib_ami06).
Can you suggest an alternative or send me a link to download it?
Many thanks!