NAND Gate Layout Design: A Complete Guide with Cadence Virtuoso | DRC & LVS Validation Included!

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  • Опубликовано: 13 дек 2024

Комментарии • 6

  • @SyedaRaheenBukhari
    @SyedaRaheenBukhari 20 дней назад +1

    Drc rule file doesnot appear when I try to paste the file path what could be the reason?

    • @SuccessPointForEngineers
      @SuccessPointForEngineers  9 дней назад +1

      Either Assura is not configured or file doesn't exist in the first place. It will have the extension .DRC or .RUL. Check if it is present or not?

    • @SyedaRaheenBukhari
      @SyedaRaheenBukhari 9 дней назад

      @@SuccessPointForEngineers Thankyou it is present

  • @MrIyan619
    @MrIyan619 5 месяцев назад +1

    Hello, did you do a layout example for Ring Oscillator and do simulation based on layout result?
    If don't, would you mind to make it, I think that would be really helpful for us. Thank you

    • @SuccessPointForEngineers
      @SuccessPointForEngineers  5 месяцев назад

      No I haven't done layout for ring oscillator. I will do that soon. Thanks..

    • @MrIyan619
      @MrIyan619 5 месяцев назад

      @@SuccessPointForEngineers Thank you so much. I am really enjoying your video. Looking foward for your another video.