the bindkey is "A"/ say you want to move/align right side of instance "x" to next to left side of instance "y". press "A" and then go to right side of x click there and then click on the left side of "y".
Could you make a video generating the hierarchical structure and making layouts at each level? Each level may have 2-3 transistor that's not a issue. Just to cover the hierachy and use of global signal. Thanks
Sir.. while doing LVS...it has showed two errors..For GPDK 45nm 1.Device g45n1svt MOS on schematic is unbound to any layout device. Similarly for pmos 2. Device nmos1v MOS on layout is unbound to any schematic device. similarly for pmos. How to eliminate them... Thank you.
You have to read the documents of your foundry file, and based on those we can select the appropriate metals for making the desired capacitor. Moreover, which application you are going to use this capacitor. I meant like RF applications or for general purpose.
Sir ..i was expecting layout from one by one layer .....like for NOT Gate we need following steps..please do it in this way .... pmos n-well ----nWell drawing p-implant --------Pimp drawing oxide layer contacts metal connection polysilicon for gate nmos p-substrate already..... n implant ---Nimp-drawing oxide layer contacts metal connection polysilicon for gate power cell vdd n-well n-implant oxide layer contact metal connection gnd p-well p-implant oxide layer contact metal connectiuon
This procedure we used in earlier versions of cadence (IC514) and it is time consuming also. Now, we can directly generate our instances in latest versions. So ,there is no need to do like this. I believe you are using old version of virtuoso. Anyways, I will upload one tutorial regarding how to make a transistor using metal layers soon.
I have completed upto DRC sir after that, i am unable to get popup window and LVS successful completed, could you help me sir
I have a question..In UMC 18, If we want to connect the bulk to any other input. How can we do this?
You can connect it by doing the normal connection only you may need nwell/pwell around that specific transistor
Sir i don't have pdiff, what i have to use sir
You can create one on your ow or guard ring can resolve that also
How to creat it sir
what keybind are you using for that snap align function? That is super useful.
the bindkey is "A"/ say you want to move/align right side of instance "x" to next to left side of instance "y". press "A" and then go to right side of x click there and then click on the left side of "y".
Could you make a video generating the hierarchical structure and making layouts at each level? Each level may have 2-3 transistor that's not a issue. Just to cover the hierachy and use of global signal. Thanks
Unfortunately, I don't have access to academic licenses so can't demonstrate that.
You can mail me for further discussions
Thanks for prompt reply. I don't have your email. Mine is amiramu10@gmail.com. Kindly send a hello msg then we can discuss.
Which techbolgy used?
I have used UMC 180 nm CMOS technology. The techniques discussed in the tutorials are the same for every design irrespective of the technology used.
Sir.. while doing LVS...it has showed two errors..For GPDK 45nm
1.Device g45n1svt MOS on schematic is unbound to any layout device. Similarly for pmos
2. Device nmos1v MOS on layout is unbound to any schematic device. similarly for pmos.
How to eliminate them...
Thank you.
Thanks Bro
And also How to Make Capacitor in cadence?
You have to read the documents of your foundry file, and based on those we can select the appropriate metals for making the desired capacitor. Moreover, which application you are going to use this capacitor. I meant like RF applications or for general purpose.
Sir ..i was expecting layout from one by one layer .....like for NOT Gate we need following steps..please do it in this way ....
pmos
n-well ----nWell drawing
p-implant --------Pimp drawing
oxide layer
contacts
metal connection
polysilicon for gate
nmos
p-substrate already.....
n implant ---Nimp-drawing
oxide layer
contacts
metal connection
polysilicon for gate
power cell
vdd
n-well
n-implant
oxide layer
contact
metal connection
gnd
p-well
p-implant
oxide layer
contact
metal connectiuon
This procedure we used in earlier versions of cadence (IC514) and it is time consuming also. Now, we can directly generate our instances in latest versions. So ,there is no need to do like this. I believe you are using old version of virtuoso. Anyways, I will upload one tutorial regarding how to make a transistor using metal layers soon.