Cadence IC615 Virtuoso Tutorial 5 (HD): Post Layout Simulation, Comp & Finding no of Parasitics
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- Опубликовано: 13 янв 2017
- This tutorial demonstrates the procedure for Post-layout simulations in Cadence, and finding the number of parasitics in our layout
Heyy.. I'm having offgrid error while layout... is there any solution for this??
Set the snap spacing (X n Y) in the display options according to the DRC Rule file.
If You see the .rul file for DRC in assura folder.
Search for off-grid in that file..the snap spacing will be define there. take accordingly that value.
in. rul file of drc.. snap value is 0.005.... is it possible to change the value to 0.001 ??????
Actually it should. I have never changed that
You may try and let me know if that works properly.
it works. and now I don't have offgrid error any more... it occurred due to the changes in X and y values...what's the next step after drc and LVS.?
Go for RC extraction and post-layout simulations.
then the gds file (if planning for fabrication)
Heyy man its alot but I don't have any other option....do you know how to do transistor sizing of 15 transistor in analog circuit..?????
hii sir i want to know how to calculate output imp. of the current mirror circuit
and why it's important to create templates and tapcell before layout of mos..... I'm having offgrid error here also....
Hi All... can anyone suggest a free technology library for analog design?
If you can access to cadence community online... You can find gpdk (generic pdk) which you can use for your design. You can download them, they are free since you have cadence login credentials.
Sir..I want ur help.please reply me
My cadence version is a bit old, so it does not have ADEL X and ADEL XL. However, in ADEL part, there is a corner analysis part and it requires to upload PCF or DCF file for simulating. I uploaded a PCF file, although it does not work. Is there anybody who has the same problem and can guide me or share me some useful documents?
The PCF aren't related to the cadence version, infact are defined by the technology. Even we can do the corner analysis in ADEL in >IC615, only thing is I have to do simulations individually for each corner. In the model files, are you selecting the corners properly and whether the model files are correct.
Error or a snapshot would have helped!
@@MudasirMir7
Thank you very much Sir. I tried this way and changed all the model libraries from "tt" to "ff"; it works, but for post-layout simulation, does it work still? I mean does this solution work for post-layout simulation?
Thanks in advance
Yes, of course!
@@MudasirMir7 Thank you very much sir.
how to make capacitor in layout???
hey, sorry for late response...
same like we create transistors...only thing is we use higher metal layers.
Mudasir Mir will you plz make one video on that.... like I want to create 10fF capacitor then??????
gr8
Sir..my pre layout and post layout is mismatch. I tried inverter aslo.but pre layout & post layout mismatch. I am using SCL PDK. I don't know why it is coming like that
How much mismatch is there? If I remember correctly SCL pdk isn't that efficient. compared to other pdks, it will have more mismatch. #experienced!
@@MudasirMir7 sir..post layout output signal is same for input. That's is the problem sir..but cleared DRC,LVS,PEX. I did one inverter for example. I got this output.
check the netlist of post-layout simulation, if you see the parasitics. your results are correct. great!
@@MudasirMir7 sir..I did inverter sir..but i got wrong output sir..It is not inverting properly sir..but parasitics is there .I have seen it. and I have a doubt on SCL PDK. Because I am using version zero sir..but many of them using version 1. If is it possible to provide wrong output.?
Hello sir
Sir i am not getting result of post with av_extracted file my netlist not working and it didn't show anything
But without av_extracted it work
Please help me sir
Did you push the update button after changing the view? Can you share snapshots of your config view and netlist/log file on my mail. Also if you did the update after changing the view, once check in the ADEL in options (toolbar)-->Simulation-->netlist-->display (check before and after changing the views in config, remember to update also). You should see lot or rc parasitics in the extracted netlist file
@@MudasirMir7 sir please provide me your mail id
You can see it in my channel about option or write your mail here.
@@MudasirMir7 anshulthakur380@gmail.com
Please sir reply
Sir can you please share your email id? we have doubts and we request your guidance.