Basic logic gate timing diagram/ waveform of basic logic gate/digital electronics

This video is on basic logic gate timing diagram. AND logic gate output timing diagram is drawn when both the input timing diagram is given. The timing diagram of both the input A and B are applied as input to AND gate. The output timing diagram of F is drawn for inputs.

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[@digitekkeys2024]

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[@gyimahemmanuel188]

Very very clear to understand

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[@ayush-9142]

I find it helpful, Thanks

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[@user-zq6me9cg3y]

Clearly understood! Thank u mam 😊

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[@rishikumarsingh5443]

Nice video mam...

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[@krishanand3176]

aunty thank you

[@BhimalrahulDasari-fq4fu]

Madam tq very much

[@herahamid6376]

Hm ny yh mid mein q line lambi ki?

[@digitekkeys2024]

Dono me se agar ek bhi input zero hai to output zero hoga. Second input mid me zero hain isliye mid me line zero hain.

[@dk.prajapati9375]

Hindi 🤔😡