edge triggered flip flop

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[@mrak8948]

oh my god this is the most elaborated video on whole youtube. Subscribed.

[@zuhaibulhassan.]

In the case of Nand Gate S come at upper side and R at lower side mean S is connected with Qn' and R with Qn you have connected apposite you can check from M Morris Mano Book"Digital Logic and Computer Design" is it so respected Ma'am?

[@tehseenabbasbhatti3750]

wada wada love you from pakistan from the depth of our hearts abdullah mulla or tehseen

[@mohsinvvv]

Great madam u r so brilliant teacher! U r the genius! Very nice 👌

[@rahulbhaskar474]

Thanks ma'am very nice explaination. You make this topic easy to understand 👍

[@sumanshetty9438]

Very neatly explained.thank u

[@pavanambala8078]

Superb explaination

[@veerabhadrayyakalacharanti4051]

Good content mam explanation is in detail as I refered many other videos

[@pramathg272]

Very well explained..very smooth..

[@mr_rawat]

Digital electronics is hard..
Ma'am : Hold my marker. 😂

[@yushmmgamer6867]

Thanku for ur genuine efforts ma'am that culminates this topic well understood to all

[@Suneriins234]

I watch fulll advertise vidios so that I can support your effort Mam...

[@aasaanpadhaai]

To support my efforts please share my videos to relevant viewers...
and watch ads only if u are interested in those ads

[@Suneriins234]

@@aasaanpadhaai Ok Mam....You are genius

[@inktober1771]

@@aasaanpadhaai ryt mam

[@tehseenabbasbhatti3750]

@@Suneriins234 pehlay sy aram ha

[@preetham36]

this is the only video in youtube about edge triggered d flip flop, thank you mam🙏🙏🙏

[@404_notfound]

9iceeeeeeeeee...... fixed my puzzled brain 😅

[@AbdullahKhan-hu8fo]

Nice explanation ma'am 😊

[@himanshugaur6790]

Great explanation

[@noshabakhan8389]

buhut achi parhati han ap Shukria

[@yogeshjaanjadiya007]

Thanq you ma'am

[@maniys]

a Big Thank from Sri Lanka :D

[@codeshala8673]

Very nicely explained

[@hansalkothari8826]

thank you mam!!

[@drishtikurmavanshi7673]

Thank ma'am.

[@bipulsingh6232]

awesome but can u make viedeo on edge triger implementation by CMOS

[@inktober1771]

Thnku mam

[@callfordragonsf2122]

Super

[@vishveshavelectronicsengin4703]

Thank you so much ma'am, was a very clear explanation, but I have a doubt in one of the Cases which is not covered.
If we assume the output is in the SET state already and the clock is also high, if we now make D from 1 to 0, the output should still remain in the previous state. But when I tried to do it with the state shown in 14:00 of the video, it didn't work, the output went to RESET. Could you pls explain where I'm going wrong.🙏

[@utkarshjadhav7979]

Thanks a lot

[@nikhil-do4sk]

Nice voice mam ❤

[@alighias8159]

keep it up

[@soshaldahal4713]

In second nand gates there must be S at top and R below or not ???

[@aasaanpadhaai]

Actually we can do like that but in that case you will gate q=1 when s=0 and r=1

[@arnabsen4430]

Yeah, even though many text books mark it in that way, its not wrong, it further depends on what gates you used for the final SR latch. But I believe ma'ams approach is more accurate

[@biswadeepchakraborty2460]

very good explanation mam..thanks a lot

[@20muhammadbilalakmal36]

ap apna thumnail acha banaia thum sbscribers zada ho ga

[@RajuKumar-vg5bj]

Mam aap kangana Ranaut ki tarah dikhati ho aur aapki aawaz bhi unhi ki tarah hai

[@mehmetkaanyildiz18]

dont name title english if ur video is in hindi please

[@prensudangol5539]

Exam he mera jaldi batana suscribe ye kya kar le time waste karte ho !!😠