Introduction to JK flip flop
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- Опубликовано: 17 фев 2015
- Digital Electronics: Introduction to JK flip flop.
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Learned more in 20 minutes of these videos than a full month in my CMP ENG course. Life saver.
Now what are you doing in ur life?
@@last_time_I_pooped_was I'm a working electrical engineer and pursuing my PhD.
As an added note, I've never mentioned, used, or required knowledge about JK flip-flops since the computer engineering course at the time of the above comment. Everything is based on the D flip-flop.
@@last_time_I_pooped_was i was wondering this too
how in the world did you not learn about flip flop circuits
Pretty Dumb I guess
After doing a couple of hour of observation and trying different combination of gates for flip-flop I came up with these conclusions.
Things get really confusing when we moved to the J-K flip flop.
Let’s start from beginning,
We’ve two data storing elements i.e.
1: SR NOR Latch
2: SR NAND Latch
They work the same but their truth tables are completely opposite to each other. i.e.
SR NOR Latch truth table
S R Q
0 0 Memory state
1 0 1
0 1 0
1 1 Not used
SR NAND Latch truth table
S R Q
0 0 Not used
1 0 0
0 1 1
1 1 Memory state
After studying these basic memory elements. We moved to SR latches with “enable”. This enable is input to the two NAND gates along with Set and Reset (as in the circuit diagram shown in video). The output of these two NAND gates is input to the Latch (SR NAND). If we replace “enable” by “Clock” we would have a flip flop.
Let me ask you a question. Can’t we use any other combination of gates?
Of course, we can.
See the possible combinations which will work as an SR flip flop.
1. AND-NOR
2. NOR-NOR
3. OR-NAND
4. NAND-NAND (Used in video)
You must be thinking what about the other combinations?
5. NAND-NOR
6. OR-NOR
7. AND-NAND
8. NOR-NAND
These combinations (5 to 8) will not work as flip flop. Try making truth table for each of these combinations. After making truth table, You’ll realise that these circuits (5 to 8) are automatically going into “Invalid State” when the clock is Low/High depending upon the circuit configuration. Flip flop must follow one property, if clock goes Low or High, it must have a memory state. See these circuits
are not storing data we can’t use these combinations.
The only possible combinations which will work as an SR flip flop are:
1. AND-NOR
2. NOR-NOR
3. OR-NAND
4. NAND-NAND (Used in video)
Hope, it cleared your doubt till now.
But as we move to J-K and T flip flop. We again have some limitations.
We get J-K flip flop when we feedback Q’ to the top NAND gate and Q to the bottom NAND gate
Using this type of arrangement of feedback. Only two possible combinations will work i.e.
1. NOR-NOR
2. NAND-NAND
Did you see? We started with 8 combinations and end up having only two useful combinations for J-K and T flip flop.
If you want to use the remaining combinations for J-K and T flip flop
1. AND NOR
2. OR NAND
Then, these two combinations can also be used if we make some changes in the feedback arrangement.
Suppose, if we have an AND-NOR SR flip flop we want to make JK flip flop then we have to use this configuration,
“If Q is input to the top AND gate and Q’ is input to the bottom AND, using this configuration the remaining two (AND-NOR, OR-NAND) will also work.”
I tried every possible combination and their truth table. Everything in this video is correct and accurate.
Hope it helped you!
your stuff is kinda wrong in terms how it is tought in my school. Here truth tables are the same with any gates, what changes are the inputs and the scheme
IE in SR latch with nand if you give top input s and bottom input r while top output is q
then you will get the opposite of regular truth table however in my university that is considered a nonsensical trigger. You have to give both inputs reversed, so top input is 'not s' bottom is 'not r' ;;;; outputs: top 'q' bottom 'not q'
though there are other combination where the table would be correct as well IE
nR->nQ
nS->Q
and only difference of sr and jk is the 11 in sr is undefined and in jk is reversed.
Wow great..... excellent understanding
😨
thanx saved me a lot of time
Bhai logic gates ki sale lagi thi kya
I had digital electronics paper today..al I did ystrdy was watching ur videos.and im nw here typing my gratitude. thank you so much brother...you have brought satisfaction in me.cos I really feel having learned something.
u r simply amazing! i hope you get all the success u deserve
I have tried to understand JK flipflips for 15 years now and FINALLY I understand what they are, An SR latch with an extra feature ! TOGGLE. My goodness, THANK YOU !!
I dont understand .why it is getting dislikes..you are getting a great job sir..with a great teaching
because he calls latches flipflops
There are teacher of our college who didn't explain
@Prateek Patel okay. I'll watch .
Dislike are from those teachers who were expelled for not teaching well...
RUclips removed dislike are you happy now ?
thank you so much for putting this much efforts and making it very clear and I'm really hoping that you are going to upload the the sequential circuits designing and analysis and the state digram because I have exam this week and can't find any good resources
Man, i just wanna thank you for your videos, they helped me out in Varsity...i graduated last year but, Thank you so much💪💪❤
At 2:04 we have the truth table for Sr ff with nor gate but we are using the diagram of Sr with nand gate these two totally gives different outputs
yes same doubt..
that is sr filp flop with NAND gate and that is correct. you are talking about sr latch with nor gate.
explained....the whole concept in a very simple manner,..... thank u sir.....
for anyone having trouble remembering this, i suggest you think of it like this: Only when Q = 1, the device can be Reset, and only when Qn = 1, the device can be set. Just as a tip for remembering it more easily 😊
Wow, your presentation was really helpful! Thanks :)
Man, you are awesome. I'm studying for my test and you are the only guy that I understand!
thank you so much for helping me.
I'll drop my PayPal contribution on your website tomorrow. keep the great work!
Great Explanation, one in a million!
Thank you very much!
That was a wonderful presentation! However, I do wanna point out that there are two main variations on the SR Latch (which are used to synthesize the JK Flip Flop)...refer to the previous video as self-evidence. WHY DOES THAT MATTER? ==>> The NOR type preserves the memory state of Q, Q_bar whenever S = R = ‘0’; S = R = ‘1’ results in the forbidden state. The NAND gate simply inverts the relationship, where all ‘0’ is forbidden and all ‘1’ is the memory preservation state. I noticed that the SR schematic is NAND based, whereas its truth table is NOR based...an alleged contradiction, if you will. I’m not a seasoned pro at this, but I think my observation makes sense, and can be used to improve the insight that you provided. Again, great video, (& to the viewers, take the presentation with a grain of salt). :) I’ll keep watching, Neso Academy. Have a great day!
+Oswald Chisala this is really confusing me how can we use NAND based rs F-F while using NOR based f-f ??
Sir you are a legend. I hope you get very successful in your life!
Thank u sir for providing such a nice explanations on the sequential circuits..it is really helpful to Me..
type sht
+ Neso Academy how did u know what is the value of Q and Q' , accept the last case where u assumed
U don't but if u see the nand truth table when ever one input is 0 then irrespective of 2 input we can say the output will always be 1.so if J=0 and K=1(0,1) input we take the Q=1 and then we pass this 1 as 2nd input of k and thus ~Q =0.
Hope this help
In J-k flip flop you have made use of 3 input NAND gate with 1.J 2.clk and 3 .k
Until and unless we get all.3 input how will the gate work or there is previous some Q and Q bar going in 3 input NAND gate , please clarify it
Sir, I am very thankful to you for this.aapke lectures se Maine bahut ache marks obtained kiye.warna meri reappear thi sir electronic mein.thanks sir......
PLEASE MAKE VIDEOS ON DIGITAL LOGIC FAMILIES (TTL, ECL, CMOS etc) and ADC and DAC conversions.
Your lectures are great.
Thank you so much for them.
he wouldve done them if you weren't screaming at him. thanks a lot.
THANKS A LOT, ITS JUST GOT ME READY.
First time i understood toggling. You are legendary man🙏
Thnku so much for making this things so easy for us☺ u were a life saver to me😊
Thank you so much sir. You are simply marvelous.
I have a question. Initially you had shown a S- R Flip Flop with S and R as two inputs with clock pulse present. That indicates that the NAND gates present in the first level are two input NAND gates.
If this is the case then how a third input (Q or it's complement) can be added as one more input to these NAND gates? In this process the two input gates are changing to 3 input gates.
yes.. it can be done.. we have a separate IC for three input NAND gate (IC7410)
thanks sir.
that's so better explained as compared to others
"you have already
studied about the SR flip-flop and D flip-flop so what is the need to study the next type of flip-flop that is your third flip-flop"
YES EXACTLY WHAT I'M THINKING, WHYYYY
Thanks sir, All your lectures are well explained. Thanks :)
you took j=0 k=1 as similar to sr flipflop
can you explain it on jk directly how it is coming that output ...without taking reference of sr flip flop..
Exactlyyyyy !
i need to understand that
Here,T.T. for SR f/f using NOR gate and and the diagram for RS f/f using NAND gate, which is quite overwhelming if you are looking table and the diagram parallely , so nerds don't get confused 😕
hello there . i do have a very simple questions at 5:30 you said when we have 0 and 1 in SR latch the result actually is that Q =0 and not to 1 based on the table you have on your presentation any answer would be helpful .
marouane bicher you have to refer to basic SR Latch table . When Reset = 1, Qnot=0
@@munirahmoorman3602 thanks bro
Iam too wasted my time there
this was grately helpful. I had a hard time understanding toggling
amazing job man! keep going !thanks for the help!
I think you are the reason for my success !!!!!
Thanks again and again sir for your work
Thankuuuuuu sir
You really help us alot.
Clear concepts in a seconds.
You really make difficult subjects easy.
Hi Neso Academy, your videos are really help full, thanks for the easy explanations.
for the JK flip flop i have a question, why are we considering the output of clk, S and R as Q(n+1) and why not just Q?
this is causing a lot of confusion since the value iof Q and Q(n+1) are opposites. please help !!
Both are same
yes
Your lectures are very helpful.
I understood the concept well thank you so much sir👍
Just discovered these lectures. Now I don't have to worry about my CC V
Don't you think so, that clk. Must be edge triggered (as per diagram) ?
I wish i found this channel sooner. finals are coming up.... gonna watch a few vids to save my grade loool
It was really helpful
I apperciate your work!!!!
Tq sir.this videos are very usefull to me.any one cam understand ur lecturing easily. Way of teaching i loved it thanq sir
00:06 JK flip-flop provides an advantage over SR and D flip-flops.
00:51 Introduction to JK flip-flop
01:42 The JK flip-flop has two outputs Q and Q complement.
02:50 JK flip-flop and SR flip-flop have similar outputs except for the last case.
04:06 Analyzing the values for Q and Q complement
05:03 NAND SR latch can produce different outputs based on input changes
06:01 The JK flip-flop races between 0 and 1
06:58 JK flip flop output is the complement of the previous state.
EE101
thank you :3
I just want to know how would the 3rd connection (which was not present in the sr FF) affect the 1st four output, I don't understand because you filled the same as SR FF..
i have learned so much things from you thank youu you are the best
A sequential circuit has two JK flip-flops with the following input equations:
𝐽𝐽𝐴𝐴 = 𝐵𝐵𝐵𝐵′
𝐾𝐾𝐴𝐴 = 𝐴𝐴𝐴𝐴
𝐽𝐽𝐵𝐵 = 𝑥𝑥′
𝐾𝐾𝐵𝐵 = 𝐴𝐴′ + 𝐵𝐵𝐵𝐵
and the output equation 𝑦𝑦 = 𝐴𝐴𝐴𝐴𝑥𝑥.
Draw the state transition table (4 Marks), and state diagram (4 Marks). What does the
function do? (2 Marks)
i cant solve this by using the following process
Can you please help me ?
If I assume Qn-1 = 1 and ~Qn-1 = 0, and I also set c=1, j=1 and k = 0, then the Inputs of the last nand gates (so the one for the latch) are both 0 and 1, which would result in Qn =1 and ~Qn = 1 if you go and check the network (not the truth table).
In 3:15 I don't get why the TT for JK and SR FFs are the same. E.g. if J=1 and K=0, the output of the K-NAND equals 1 because K=0, but what would prevent the output of J-NAND from also being 1 and the latch being in memory state if neg(Q) was 0 previously ?
Is there a difference between a JK flipflop formed from an SR(using nor gates) and other SR(using NAND)?
yes
your video is awesome.. thanks a lot
salute to neso academy very good explanation
5:20 you say when input of sr ff is 0 and 1 the output is 1 and 0. but it's wrong. according to the table when input is 0 and 1 output is 0 and 1 only. o.O help
i noticed that too .... but its right for nand sr output
NAND gate 😑
kunal choudhary yes dude i got you
he is correct, notice he said "SR LATCH" not "SR ff",
Aman Deep we have to use truth table of latch and not flip flop
Congratulations 👏👏🎊 sir for 1million subscribers , keep growing
Uyyyy7w
You are amazing. Thank you!!!
you guys are great. iam able to understand about flip flops. good job. all the best guys and thank you : )
Thank you very much for uploading these videos. Now I am able to understand digital electronics a bit.
But Sir, will you please do me a favour by uploading the positive and negative edge triggering of SR, D, JK and T flip flops because I am not able o understand these particular things in digital electronics.
Thank You.
good clear explaination,thank you
are you trying to tell me, with a JK flipflop and two high inputs, it will flipflop?
Madness!
PS, actually very helpful. Thankyou :)
Thank you so much, sir.
for me this tutorial is so good good job
just awsome video tutorials....i have ever seen...@neso
sir in the sequential circuits playlist, you haven't added video of characteristic and excitation table of d flip flop.You directly moved onto JK flip flop. Please add it to the playlist too.
Excellent video!
Sir can you make a series of videos on 8085 microprocessor please!!!...and thank you for your existing content too
1:00 Why does the logic diagram represents a SR flip-flop with NAND gate but the truth table is of a NOR gate SR flip-flop?
that was rly helpful, thnx
sir while write output for inputs your not condidering q and q' inpus just writing outputs considerin only j and k and enable or clock
sir I think there is a mistake. during the second round you have 1 at the input of upper right nand gate and 0 through Qbar. so the output should be 1and not 0. please explain. thank you
Yes . The guy messed up there .
hello
can you tell how to solve this problem
q)Consider a J K' flip flop i.e., J K flip flop with an invert er between the external input K' and the internal input K
sir how can we assume ourr self the value of Q (4:20)
the value of Q will depend on the previous state before input becomes 1,1 . so the Q value doesnt matter, it could be 0 or 1 but the working will be same
Man, you are awesome.
I have not understood your tt which you have used as ref of sr flip flop. in earlier lecture it was diff
viraj jarande clearly shows that you just skipped the video that you shouldnt skip
@@munirahmoorman3602 no bro, the problem is that in the video, he is applying the truth table of a 2-input nand gate to a new 3-input nand gate and thats Wrong!
How are you telling that 2nd case will be same as SR ff. while clk=1 j=1 how do you know what will be the value of Q'? and you decided to put as same SR ff?
Sir when the CLK is low the circuit will get off by having the previous outputs in memory but why get J* and K* as 1..
At 2:40 in the video
I have a question...
Is this possible to work with nor instead of nand ?
In that case,can i use Q of any J-K ff as clock signal?I mean for J=K=1
the memory condition for sr nand latch is q=1, q'=1. and here you have used the memory condition for nand latch as q=0,q'=0. and if i try to implement jk flip flop for nor gate using its memory condition, which is q=0,q'=0 , this does not seem to work. Am I wrong somewhere? please help me out if anyone can.
Great explaination sir I was totally understanded thank you for sharing this sir♥️👌
Hi, thanks for the video. I have a question. Why is the truth table for an SR NOR gate flip flop when the SR flip flop in the diagram is a NAND type? Thank you.
Exactly. I was confused as well. Can someone explain?
So what do the JK, D, SR and T flip flops do in general? Do they control the amount of duty cycles in a wave, change the waveform, etc... ? I am still a little confused.
Have you figured it out because I'm also confused
@@maxbreaker which part are you confused on? I might be able to help
for rs latch using NOR and NAND is totally opposite but here they used SR latchnor gate truth table with sr nand gate icant able to under stand
can any one explain me ....
I m watching almost every 6 months
simple to understand videos!
awesome videos..helped a lot..thank you
What did you use to make the video? I mean if there's a specific software other than a lightpen ^ ^''
Even i want to know
so you explained the jk latch but how do we use jk latches to make JK flip flop?
Happy teacher's day...Sir. Your videos helps me a lot. Please make video on electromagnetic.
sir, in 2:57 why you considered that when j= 1 , k=0 is same as SR flip flop ?
well that's just awesome thanks
sir, i had a doubt. In this video you have used the NAND gate SR flip flop but the truth table you have used is of NOR gate SR flip flop. Please tell me why so?
Thank You.
@neso academy ..i also have the same question?plz answer
It's true that SR flip flop is of NAND gate but that truth table is not of NOR gate SR flipflop , It is truth table of SR flipflop using NAND gate only. You are confusing this truth table with SR patch using NOR gate as both give same visualization.
P.s: I know this question was asked 1 yr back , but it might help someone, so i'm writing .
tnx
It'll help her in her KT Exam
Why so confuse ? This means you skip the parts that you shouldnt skip and came out of nowhere watching this part. 1 1 is memory for NAND SR LATCH but this truth table is for SR FLIP FLOP. There is extra 2 and gates infront of those basic latch. So the truth table is different from the NAND Latch
Isn't the truth table you have for the SRFF for the nor gate implementation?
at 5:21 both nand gates in the second set are recieving 01 so both their outputs should be 1, no?
David Stern well ur doubt is correct but actually the mistake u r doing is that u r taking both the feedback values simultaneously dont do it simultaneously first take one feedback at a time and let the value of the one output change then take that changed new value as the feedback value for the other nand gate.You will get the correct answer.but here also start from the upper flip flop and not from the lower flip flop take the feedback that upper flip flop is getting get the new output and then take it as a feedback to lower flipflop.
the reason for this is that nomatter how similar two flip flops are they always has some speed difference in them which is of the order of picoseconds so we have assumed here by taking q=0 and !q=1 that the upper flip flop is faster so it will get the feedback first.....hope ur doubt is cleared now
can i use it for blinking of two leds?
Explaination method is excellent
I don't know why you have choosen as Q and Q complement different in last case... What does the meaning of last state if you taken as Different ? I don't know why... But I think there should be some different explanation to it....
Life Saver! Thanks a lot
Whether the race around condition is the output Qn cannot be predicted at the end of the clock pulse.?
u explained jk flip-flop using NAND gate .. in my book it is explained using AND and NOR gate .. and now i m totally confused .. what 2 do?