STA_L1e -Timing Optimization During Logic Synthesis

To understand the importance of STA, it's very important to know VLSI Design flow and how different timing checks are required at different stages.
In previous video:
STA_L1a: I have discussed generic VLSI Design Flow. (Link of previous video : • STA_L1a - Overview of ... )
STA_L1b: I have discussed generic Overview of VLSI Frontend Design Flow. (Link of previous video : • STA_L1b - Overview of ... )
STA_L1c: I have discussed generic Overview of VLSI Backend Design Flow. (Link of previous video : • STA_L1c Overview of VL... )
STA_L1d: I have captured the importance of Timing Analysis From RTL to Logic Synthesis. (Link of Previous Video : • STA_L1d - Importance o... )
In this part - I am discussing the Timing Optimization Flow during Logic Synthesis.