Hi Jim, I am watching a lot of your courses , i would like to thank you for all the high quality courses , one more thing man " listening to you is like a rockstart singing science !!!! you should really think about radio/voice over career" :D
One clock cycle to load all the data into the flip flops via the combinational logic of AND/OR gates. And since it's a 4 bits, to fully get the transfer out those 4 numbers, it takes 4 clock cycles as they are serially passed> > > >
Hi Jim, I am watching a lot of your courses , i would like to thank you for all the high quality courses , one more thing man " listening to you is like a rockstart singing science !!!! you should really think about radio/voice over career" :D
oh those logic circuit faces, they always crack me up! 12:20 Great video btw. As always.
I understood this perfectly! THANKS!
So if I'm correct, the data first gets loaded in by the "load-mode" and then gets shifted to the end ?
One clock cycle to load all the data into the flip flops via the combinational logic of AND/OR gates. And since it's a 4 bits, to fully get the transfer out those 4 numbers, it takes 4 clock cycles as they are serially passed> > > >
you are great
excellent
i think D0 will cause an error if its alue isa one !