Dear Professor, Please, could inform me if I can simulate ( OECTs ) " Organic electro chemical transistor" with LTSPICE. If you have a nother possibility to simulate this devide, please, inform me. Best wishes
Thank you Professor for your rsponse. Please, I need the OEFET file spice if you have the link to insert it in my library . Thank you for your help and your collaboration. @@dr.hariprasadnaikbhattu
hello hari sir do you remember me i am the same guy who asked you some questions of designing the layout of 3bit ripple carry adder . i have imported nand gate layout directly for designing of xor gate layout as it contains four nand gate but i am getting error of metal and metal crosssection in cadence again and again and i am unable to manage the metal vs metal crosssection error all poly joining are inside the nand gate layout and outside of that there are many metal metal joining but they are getting intersected .please tell me what should i do .
Before your reply my mind have got that idea 💡💡💡 but tell me sir I have used metal1 for input A and B in nand gate layout then for xor gate which contains 4 nand gate I have to make two another input let's suppose Va and Vb so if I make va and vb metal2 and metal 3 then while connecting to input A and B I have to use via metal2tometal1 and metal3to metal1 right sir
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thank you, it helps a lot.
Welcome
Dear Professor,
Please, could inform me if I can simulate ( OECTs ) " Organic electro chemical transistor" with LTSPICE.
If you have a nother possibility to simulate this devide, please, inform me.
Best wishes
Hi, is the OECT a mathematical or
Spice model. Based on that simulation can be doen
Thank you Professor for your rsponse.
Please, I need the OEFET file spice if you have the link to insert it in my library .
Thank you for your help and your collaboration.
@@dr.hariprasadnaikbhattu
hello hari sir do you remember me i am the same guy who asked you some questions of designing the layout of 3bit ripple carry adder . i have imported nand gate layout directly for designing of xor gate layout as it contains four nand gate but i am getting error of metal and metal crosssection in cadence again and again and i am unable to manage the metal vs metal crosssection error all poly joining are inside the nand gate layout and outside of that there are many metal metal joining but they are getting intersected .please tell me what should i do .
Hi, import the instance of nand gate. Not directly. Need to follow the design rules
If possible use metal 2 when there is crossing along with metal 1, metal 2 via
Yeah I have check drc and lvs both
Before your reply my mind have got that idea 💡💡💡 but tell me sir I have used metal1 for input A and B in nand gate layout then for xor gate which contains 4 nand gate I have to make two another input let's suppose Va and Vb so if I make va and vb metal2 and metal 3 then while connecting to input A and B I have to use via metal2tometal1 and metal3to metal1 right sir
Sir here PWFL file we need to create
Yes, see the process through which i have created