Hello sir, I have used the same parameters used in the video, I have used gpdk180 for the schematic diagram and I created a schematic for Nand gates and then created a 2:1 mux using Nand gates, For the output waveform I am getting spikes, in this scenario what could be the problem?
thanks for the guidance i also have project of designing and layouting on cadence of 8:1 mux using stastic cmos logic and also dual rail logic and my project guide said to do 2:1 mux for showing him but hey says to verify truth table with output waveform of cadence but here also i can't verify the truth table what should i do ? i have got output following you but it can't verify the truth table for 2:1 mux.. can you guide or suggest ? will help alot thanks...:)
Hello sir we have vlsi project 3 bit ripple carry adder I have designed schematic diagram using symbols of xor and nand gate created by me but when I am clicking directly on 3bitrca layoutxl then connectivity ->generate I got many no of nmos pmos unconnected with each other. What should be approach to make layout for that type of big circuit. Should we first make latout for gate symbols like xor and nand gate then go for layout of 3bitrca.
i have done making the schematic but the op is not as expected and can't figure it out what's wrong so i was willing to connect with you sir, with email or any sort of social media you will prefer@@dr.hariprasadnaikbhattu
Наука
I have complete 8:1 mux due to your help thanks🎉❤
You are welcome
Sir can't we design layout for 2X1 mux?
Yes it can be designed
Thank you sir
You are welcome
Thanks
Welcome
I'm not getting output Y coreectly why?
Hi, have you connected the output or not
Hello sir, I have used the same parameters used in the video, I have used gpdk180 for the schematic diagram and I created a schematic for Nand gates and then created a 2:1 mux using Nand gates, For the output waveform I am getting spikes, in this scenario what could be the problem?
Hi, check the vdd applied or not
thanks for the guidance i also have project of designing and layouting on cadence of 8:1 mux using stastic cmos logic and also dual rail logic and my project guide said to do 2:1 mux for showing him but hey says to verify truth table with output waveform of cadence but here also i can't verify the truth table what should i do ? i have got output following you but it can't verify the truth table for 2:1 mux.. can you guide or suggest ? will help alot thanks...:)
Hi, since you got the output for 2:1 mux. Waveform is the truth table. See for high and low transition. It represents truth table
what should i take the widths when i am taking the length as 180nm?
First tell me are you designing analog or digital circuit. Analog width may change. For digital can have default width
@@dr.hariprasadnaikbhattudigital
Digital
Hello sir we have vlsi project 3 bit ripple carry adder I have designed schematic diagram using symbols of xor and nand gate created by me but when I am clicking directly on 3bitrca layoutxl then connectivity ->generate I got many no of nmos pmos unconnected with each other. What should be approach to make layout for that type of big circuit. Should we first make latout for gate symbols like xor and nand gate then go for layout of 3bitrca.
Please give reply sir
Yes create individual xor, nand layout and form the full layout
Check again once
Sir can you please provide the notes on your your 2x1 MUX design experiment.
Hi, I have used the circuit concept from text book. It is available in any form
@@dr.hariprasadnaikbhattu Can I know the name of that textbook
Sir plz can I get the information or report for this 2x1 mux it will be helpful for my project report🙏.
Sir can you make a video on 8:1 mux using static cmos logic
Hi, the process of designing 8:1 mux is similar to 4:1 mux. Use three 4:1 mux to get 8:1
@@dr.hariprasadnaikbhattu i will try sir thank you and what about the vpulse value should i increase it as you increased in that video?
@@akashkale8278 you can create your own vpulse
thanks sir i will give it a try and will let you know thanks for the guidance :)@@dr.hariprasadnaikbhattu
i have done making the schematic but the op is not as expected and can't figure it out what's wrong so i was willing to connect with you sir, with email or any sort of social media you will prefer@@dr.hariprasadnaikbhattu