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Sir plz upload video on how to design 4:1 MUX using pseudo nmos logic and clocked cmos logic and measure their power and delay in cadence tool
Hi, process of designing a mux is same. Pseudo nmos logic and clocked logic may require alternative form of circuit
Hello Sir, please upload how to design a tri-state buffer in virtuoso Sir
Sir Connect another inverter between pmos and nmos and make it as enable for on and off
Sir plz upload video on how to design 4:1 MUX using pseudo nmos logic and clocked cmos logic and measure their power and delay in cadence tool
Hi, process of designing a mux is same. Pseudo nmos logic and clocked logic may require alternative form of circuit
Hello Sir, please upload how to design a tri-state buffer in virtuoso Sir
Sir
Connect another inverter between pmos and nmos and make it as enable for on and off