Verilog Coding and Simulation in Cadence Virtuoso Analog Environment | AMS Simulation

#cadence #asics #ams #verilog #virtuoso #digital #analog

[@user-fk6yj9ys5s]

keep up the work, perfect videos.

[@VLSIToolBox]

thank you

[@mrinalkantidebnath1301]

🎉

[@bpenaval2541]

Nice video. You need to get a better microphone or get closer. There is too much echo. Thanks.