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VLSI Tool Box
Индия
Добавлен 16 дек 2010
Welcome to our RUclips channel dedicated to Industry-oriented VLSI CAD tools demonstrations! Our main goal is to assist aspiring VLSI engineers with their project work, ensuring a smooth experience and fostering a genuine interest in this exciting field. Join us as we provide insightful tutorials and practical guidance, enabling you to navigate through the world of VLSI with confidence. Whether you're a beginner or an experienced enthusiast, our channel is your go-to resource for mastering VLSI CAD tools and unlocking your potential in the industry. Subscribe now and embark on a journey of knowledge and growth in the fascinating realm of VLSI!
Part 1: How to Design Differential amplifier using GPDK90nm Technology
#analog #cadence #cadence #amplifier #design #gpdk
1: Link for How to find process parameter of any technology node
ruclips.net/video/dQ9-rNUSnX0/видео.html
2. Link for finding channel length modulation of any technology node.
ruclips.net/video/mVkYuVDWEls/видео.html
3. Link for all remaining analysis :Two Stage Op-amp design | AC Analysis | DC Analysis | PSRR | CMRR | ICMR | Noise | using TSMC65nm
ruclips.net/video/GQowMsb5pD0/видео.html
1: Link for How to find process parameter of any technology node
ruclips.net/video/dQ9-rNUSnX0/видео.html
2. Link for finding channel length modulation of any technology node.
ruclips.net/video/mVkYuVDWEls/видео.html
3. Link for all remaining analysis :Two Stage Op-amp design | AC Analysis | DC Analysis | PSRR | CMRR | ICMR | Noise | using TSMC65nm
ruclips.net/video/GQowMsb5pD0/видео.html
Просмотров: 965
Видео
Part 2 : How to Design Practical Differential Amplifier using gpdk90nm Technology
Просмотров 3065 месяцев назад
In this video practical forms of differential amplifier is shown and implemented. #analog #cadence #gpdk #mosfet #cad #vlsiprojects
How to find process parameter of any technology node | UMC180| Cadence
Просмотров 7136 месяцев назад
In this video, UMC180nm technology is used to show the demo. The value that are obtained in this video are the approximated value, anyone can use it to design any circuits initially. #cad #cadence #analog #mosfet #virtuosos
Two Stage Op-amp design | AC Analysis | DC Analysis | PSRR | CMRR | ICMR | Noise | using TSMC65nm
Просмотров 8 тыс.6 месяцев назад
This Video covers a Complete frontend analysis of a 2-stage opamp design using TSMC65nm Technology. #analog #cadence #cadencedesignsystems #tsmc #tsmctutorial #mosfet
How To Find Channel Length Modulation Coefficient Lambda using MOS Output Characteristics
Просмотров 9048 месяцев назад
In this Video how to find channel length modulation coefficient Lamda from output characteristics is demonstrated. #cad #cadencedesignsystems #cadence #analog #device #mosfet
Tutorial 2: Universal Logic Gates Design and simulation using LTSpice | NAND Gate| NOR Gate
Просмотров 32811 месяцев назад
In this video universal logic gates i.e 2 input NAND and NOR gates are designed and simulated using LTSpice. #analog #asics #ltspice #cmos #logicgates
Tutorial 1: CMOS inverter Design & Simulation using LTspice |VTC | Transient Analysis
Просмотров 2,6 тыс.11 месяцев назад
Download Link www.analog.com/en/design-center/design-tools-and-calculators/ltspice-simulator.html #ltspice #analog #inverter #cmos #asics
Part 4: Two-Stage Op-amp Layout verification and Post-Layout simulation | DRC | LVS | PEX| ASSURA
Просмотров 98311 месяцев назад
This video demonstrates the layout design verification steps using Assura tools where DRC, LVS and PEX is shown as well as post layout simulation is shown. #cadence #analog #umc #layout #virtuoso #asics
Part 3. Layout of Two stage Opamp | UMC180nm Technology
Просмотров 2,2 тыс.11 месяцев назад
This video demonstrates how to to do layout of two stage op-amp using UMC180nm technology, #cadence #analog #asics #layout #optimisation #umc #virtuoso #ams
Part 2: Simulation and analysis of 2-stage op-amp | PSRR | SLEW RATE | ICMR | POWER
Просмотров 2,9 тыс.Год назад
This video shows all the simulation and analysis of 2 stage opamp. #analog #cadence #cadence #ams #asics #layout #optimisation #umc
Part 1: Analog Circuit Sizing using Softcomputing Algorithm | AC Analysis | Gain | Phase | CMRR
Просмотров 965Год назад
#cadence #analog #asics #virtuoso #umc #optimisation Link of publication www.researchgate.net/publication/281837687_Investigating_the_switching_performance_of_an_inverter_design_using_the_Human_Behavior_based_PSO www.hindawi.com/journals/tswj/2014/194706/
Current Mirror Layout using TSMC65nm Technology with interdigitation matching.
Просмотров 2,2 тыс.Год назад
#cadence #analog #virtuoso #ams #layout #tsmc #tsmctutorial Demonstration of interdigitation matching layout using PMOS-based current mirror.
Verilog Coding and Simulation in Cadence Virtuoso Analog Environment | AMS Simulation
Просмотров 4,6 тыс.Год назад
#cadence #asics #ams #verilog #virtuoso #digital #analog
Differential Pair Layout using Common Centroid Matching Technique in TSMC 65nm PDK
Просмотров 2,7 тыс.Год назад
#cadence #asics #cadence #virtuoso #tsmc #tsmctutorial #layout #analog
PART 2: Logical Equivalence Check (LEC) using Cadence Conformal Tool
Просмотров 5 тыс.Год назад
#cadence #digital #synthesis #postsynthesis #lec #conformal #asics #rtl #asics #edatools
Standard Cell Layout Using Euler Path Optimisation demonstrated in Cadence Virtuoso.
Просмотров 947Год назад
Standard Cell Layout Using Euler Path Optimisation demonstrated in Cadence Virtuoso.
PART 1: RTL SYNTHESIS USING CADENCE GENUS TOOL
Просмотров 10 тыс.Год назад
PART 1: RTL SYNTHESIS USING CADENCE GENUS TOOL
Tools required for digital IC Design flow
Просмотров 508Год назад
Tools required for digital IC Design flow
Part 2: FPGA IN LOOP | VIO | ILA | SLICE IP CORE | BLOCK IMPLEMENTATION
Просмотров 180Год назад
Part 2: FPGA IN LOOP | VIO | ILA | SLICE IP CORE | BLOCK IMPLEMENTATION
Part 1: NEXYS 4 DDR FPGA IMPLEMENTATION
Просмотров 704Год назад
Part 1: NEXYS 4 DDR FPGA IMPLEMENTATION
Analog Mixed Signal IC Design: LEF File Generation using Cadence Abstract Tool Tutorial
Просмотров 2 тыс.Год назад
Analog Mixed Signal IC Design: LEF File Generation using Cadence Abstract Tool Tutorial
Analog IC Design Flow: Essential Tools and Workflow
Просмотров 743Год назад
Analog IC Design Flow: Essential Tools and Workflow
Part 2: TSMC65nm Technology Layout | CMOS inverter Layout | Cadence Virtuoso
Просмотров 6 тыс.Год назад
Part 2: TSMC65nm Technology Layout | CMOS inverter Layout | Cadence Virtuoso
Part 1: CMOS Inverters Made Easy with Cadence Virtuoso in TSMC65nm Tech!
Просмотров 1,4 тыс.Год назад
Part 1: CMOS Inverters Made Easy with Cadence Virtuoso in TSMC65nm Tech!
From Idea to Reality: How Schematic Design is Turned into a Chip Using SCL180nm Technology
Просмотров 1,7 тыс.4 года назад
From Idea to Reality: How Schematic Design is Turned into a Chip Using SCL180nm Technology
FPGA Based Scanning & positioning system
Просмотров 42911 лет назад
FPGA Based Scanning & positioning system
You might have disabled the dots back side .then it looks more beautiful...thank you for the video
absolutely the best video there is regarding all the simulations and setup.
Thank you
Thank you!!!
Sir, where can i get mobility and Cox values for 90nm or 180nm technology?
ruclips.net/video/dQ9-rNUSnX0/видео.html
Such a great video, deserves a million views!
greattt tutorial
pl , explain for me , pl
sure
Please explain to me why CMRR is calculated by taking x0 - x1, while the formula CMRR = log20(Ad/Ac) , thanks
Since x0 and x1 are already in dB we are subtracting
This is a property of logarithm where log of any fraction can be calculated by subtracting the denominator from numerator
Fantastic tutorial ! Your step by step approach really helps to understand the workflow. One note why not use common source and drain method in layout.
It is a common centroid layout for best matching
do you have a video tutorial on layout for beginners ?
yes inverter design tutorial ruclips.net/video/Mb3H1XCabwY/видео.html
Great information
Hello, Can we generate verilog code from layout using genus synthesis tool?
No, you can generate LEF file from layout
how can i install
i have cadance in my windows
Sir can you make a detailed video on different types of comparator design using cadence tool which will include the sizing,noise analysis and other considerations also like metastability It will be helpful to us. 🙏🙏
Sure I will try
Do you have any idea, how to simulate circuit generated using verilog code and analog circuit?.
You can do mixed mode simulation using AMS simulation process
Hello, good time How is the Limiter block designed in Cadence and is there a cell for Limiter in Analoglib?
Thank you 👍 ft=fh*A=(1/2*3.14*Rout*CL)*A A=Av=gm*Rout So ft=gm/2*3.14*CL, So gm=ft*2*3.14*CL.....
great sir , pls make a video on a folded cascode amplifier using Gm/id technique ....
yes i will
How do you simulate if you have multiple modules and and have generate statements in the module
You can write a top module upon which you can instantiate the other modules and map with the top module using structural modelling.
Great video!
Thanks!
Nice video for design a differential Amplifier.😊
Thanks for watching
How to load a particular hierarchy of golden side in conformal LEC
You have to select the top module in the golden side, and keep other sub module verilog files in the same folder
Do we have any command like how we use get_cells in dc/fc shell?
@@Gnani818 you type "get_" then press tab to get suggestions in dc shell
@@VLSIToolBox i know the dc_shell commands. my question is, in conformal LEC do we have any such commands to load a hierarchy or a cell?
Nice demo Sir. Please tell me how to choose the drain current (ID) and transistor aspect ratio (W/L) for extracting the μCox of a transistor.
You can choose Id and w/l any arbitrary value or if you want, you can choose Id value according to your required bias current in your design and w/l you can take any arbitrary value, it will give almost same value of uncox
Thanks Sir 👍
Please upload such informative videos sir🎉
Sure I will
Thank you very much for uploading this video , sir , great work and very nice explanation.
thank you
Nice work sir🎉
Keep watching
Very nice demonstration! Great 👍
Thank you very much!
Cognitive
Great
Great
Thank you so much, sir. it is very good for beginners
Why are u doing analyze setup and data path?
Analyze setup automatically resolve some unmapped points due to seq-constabt, seq merge etc
@@nikhilbathula8733 analyze setup analyze and resolve all the setup issues? Does it need svf txt or vsdc ?
If the netlist os from synopsys tool then yes a vsdc file has to be read into conformal. Conformal has an internal python script to convert vsdc file into conformal readable Svf is not required
@@nikhilbathula8733 thanks
Can you give me 4 input files like the example in the video? I need them to analyse and understand the tool. Thank you !
Nice video sir , very informative for vlsi students...🔥
Keep watching
why ac analysis for psrr and not xf
yes you can do with xf analysis
Hi sir, how to view the waveform of capacitor charging?
Connect slightly higher valued capacitor to inverter circuit and run transient analysis, you can view the capacitor charging discharging
Thanks for the video! I think that you might have chosen ABBA for randomness but since it is a current mirror, the diode transistor is better placed in the middle based on what I have seen in other explanations :)
ABBA is chosen
Dear sir, How to create automatic layout from verilog code. Sir Can you make one video please
yes keep watching it will be coming soon
Thank you! it was very helpful
You're welcome!
Video is very useful sir
Keep watching
Thankyou sir
Thankyou sir.
Most welcome
Good explanation and demonstration keep it up Sourav
Thanks a ton
Superb video of analog Layout design....
Thank you
When I do extraction, it getting stuck at 0%, how can I debug this
There may be problem on installation or supporting linux file or the input file given to the abstract tool
can you pls share the doc file of the same , i need tuts for genus , jasper gold and xcellium cadence tools
if you have the login to cadence support you can get Rapid Adoption Kit (RAK) file for genus and other tools download it and check the manual and also script file given in the RAK
Nice video. You need to get a better microphone or get closer. There is too much echo. Thanks.
Good explanation keep it up
Thank you, keep supporting
Can you send the kibrary of TSMCN65 if it is possible?
No, it is not possible as we have signed an NDA with TSMC.
👍