PART 1: RTL SYNTHESIS USING CADENCE GENUS TOOL

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  • Опубликовано: 12 авг 2023
  • #circuitdesign
    #RTL
    #digital
    #cadence
    #rtl
    #genus
    #synthesis
    #verilog
    #netlist
    This video demonstrates the essential RTL synthesis steps using the cadence genus tool.

Комментарии • 8

  • @ravindrakumar-xe7bm
    @ravindrakumar-xe7bm 10 месяцев назад

  • @LongPham-rh4cp
    @LongPham-rh4cp Месяц назад

    Can you give me 4 input files like the example in the video? I need them to analyse and understand the tool. Thank you !

  • @user-ut5bu9yo2k
    @user-ut5bu9yo2k 6 месяцев назад

    can you pls share the doc file of the same , i need tuts for genus , jasper gold and xcellium cadence tools

    • @VLSIToolBox
      @VLSIToolBox  6 месяцев назад

      if you have the login to cadence support you can get Rapid Adoption Kit (RAK) file for genus and other tools download it and check the manual and also script file given in the RAK

  • @debayanchatterjee9444
    @debayanchatterjee9444 8 месяцев назад

    How to install the cadence genus tool

    • @VLSIToolBox
      @VLSIToolBox  7 месяцев назад

      You can contact me through mail

    • @debayanchatterjee9444
      @debayanchatterjee9444 7 месяцев назад

      @@VLSIToolBox please provide you mail ID I will contact you for sure

    • @debayanchatterjee9444
      @debayanchatterjee9444 7 месяцев назад

      @@VLSIToolBox or if you want I can provide you my mail ID