CombCkt - 6 - Parasitic Delay

[@kishanbaranwal8331]

Love u sir from pakistan

[@ofek2852]

I think at 5:50 there is a mistake in rise delay calculation. he considered the total resistance as R, but he should have related it as parallel resistance, thus the 1/RT=1/R1+...1/Rn.
it also makes sense because there are a lot of pmos which will charge those caps, so the delay shouldn't be so high...

[@SUNNYKUMAR-qv4ki]

arent we considering only one PMOS pulls thereby offering the max resistance instead what you said should contribute to contamination delay

[@prakashkumar833]

Sir, at 23:16 what normalization means, the value we are getting is 3 for Nand-3, but the propagation delay is 7RC. How we can relate both ? Please clarify

[@captainstreamer3261]

Sir , wanted to say as we need to increase drive to charge large capacitance at output, we are going to upsize it , and finally after upsizing when we get the total capacitance this parasitic capacitance is soo small ( because it does not depend on upsizing ) and additive term that we could neglect it, so we don't need to bother after upsizing,, all we need to get a normalized factor of parasitic delay that we can get to compare diffusion cap only at the output node instead of getting it from every junction node, and how we get normalized factor, ans - devide the output diff.cap of Original circuit with the reference model output diffusion cap..

[@pawansharma6226]

​@@captainstreamer3261 I read you comment several times but Still I don't get what you want to say!!!!!
We don't need to bother after resizing.
Bother about what? " Parasitic Delay , Right?"
I get it.
But what is the purpose of finding "Normalised Factor of Parasitic Delay?". What is the purpose of it.???

[@LamtiFocus]

@@pawansharma6226purpose is that we don’t have to do so much calculation for finding the parasitic delay again and again. Normalising parasitic delay is much easier and time saving

[@suryabheemesh3199]

We are sizing the transistors to get the equal rise and fall delays. But after calculation, Delays are unequal.

[@ofek2852]

No. We're sizing it to achieve an appropriate charging/discharging load capacitance.
the differences of fall/rise delays occur because of different resistance. The motivation was to get worst case resistance of max R. but not to have equal resistance...

[@nityanand_]

Many times sir have said
You can check this in simulation (at these 20nm nodes)
Which software is being used at IITM or wherever, please let me know if any of you guys watching this vid knows.

[@vasanthrajkirubhakaran9617]

Cadence Virtuoso

[@nityanand_]

@@vasanthrajkirubhakaran9617 no they used open source there, friends from IITM told me this

[@AbhishekSingh-up4rv]

@@nityanand_ Which open source bro?

[@chetanggs]

@@nityanand_ hey I guess they use PSPICE , based on what I have heard

[@nicoyu9]

大哥你是不是磕了点啥？