13:49 Well , I did something different for NOR2 to get alpha=4. We know for a reference Cmos , Pull up network has worst case Resistance= R/2. So , considering wodth to be alpha for Each PMOS in NOR2, Total Resistance of pull up= (R/alpha + R/alpha ) = 2R/alpha. so 2R/alpha = R/2 so Alpha = 4. Is this Approach Correct??
No sir, your initial assumption is not right. the worst-case resistance of PU in CMOS is R. (For w/alpha=1 the resistance is 2R, but for w=2 the resistance is R)
Thank you, sir, for sharing this video. I want to ask about sizing PMOS and NMOS transistors equally in a transmission gate in digital circuits. When someone sets the sizes as (W/L)n=(W/L)p to achieve higher speed, I'm unsure about the reason behind it.
I'm not sure of the "higher speed" you mentioned. But I'm certain this is not necessary to make the pmos twice wider than the nmos, because now they are not connected in series, but in parallel. most of the time, both of them conduct together.
It is just an examples to show the width can be different and still we can get the same resistance R, so which width is suitable, we can also make width to be 8,8,4:: 16,16,8 and so on
He mentioned several times "worst case of PD/PU path". according to that, in case of the nmos PD, one should make it lesser resistive, unlike the pmos PU. still, it doesn't fit with intending to have a normalized delay as the CMOS inverter... in fact, there is a limitation with normalizing it. for example, try to normalize it in NAND3. (You (apparently) can't because you don't have a pmos less then w=1...)
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13:49
Well , I did something different for NOR2 to get alpha=4.
We know for a reference Cmos , Pull up network has worst case Resistance= R/2.
So , considering wodth to be alpha for Each PMOS in NOR2,
Total Resistance of pull up= (R/alpha + R/alpha ) = 2R/alpha.
so 2R/alpha = R/2
so Alpha = 4.
Is this Approach Correct??
No sir, your initial assumption is not right. the worst-case resistance of PU in CMOS is R. (For w/alpha=1 the resistance is 2R, but for w=2 the resistance is R)
Great sir!
For pull up network in the last example how sir have chosen A = 4 and B = C = 4 ??
Thank you, sir, for sharing this video. I want to ask about sizing PMOS and NMOS transistors equally in a transmission gate in digital circuits.
When someone sets the sizes as (W/L)n=(W/L)p to achieve higher speed, I'm unsure about the reason behind it.
I'm not sure of the "higher speed" you mentioned. But I'm certain this is not necessary to make the pmos twice wider than the nmos, because now they are not connected in series, but in parallel. most of the time, both of them conduct together.
At 17:35
Why sir has taken B=4, C=4 and D=2 ?
It is just an examples to show the width can be different and still we can get the same resistance R, so which width is suitable, we can also make width to be 8,8,4:: 16,16,8 and so on
@@siddhant-x8k still dont understand. i understood the alfa= 3/2 part. But what is the even values with the red(2,4,8). what are they depend on ?
@@saygod3755 if WB=Wc=4, WD=ALPHA, then RB=RC=R/4, Now path BCD: R/4+R/4+R/alpha=R(reference worst case) . Solves to give WD=2
If we consider the other path to calculate the width then A and D are 2 thus B and C are 4. (Ignoring Worst Case method for calculation)
if taken your reference then area will be large . but we want area as minimum as possible
why not pmos size is 1 for NAND2
He mentioned several times "worst case of PD/PU path". according to that, in case of the nmos PD, one should make it lesser resistive, unlike the pmos PU.
still, it doesn't fit with intending to have a normalized delay as the CMOS inverter...
in fact, there is a limitation with normalizing it. for example, try to normalize it in NAND3. (You (apparently) can't because you don't have a pmos less then w=1...)