3:28 When we upsize the NMOS to reduce resistance hence fall delay, how is the logical effort increasing. Suppose if we size NMOS from 1 to 2. For gpd, we compare logical effort with an inverter with same drive strength i.e. nmos with size 2 and pmos with size 4(since symmetric cmos inverter). If we calculate gpd - it comes 2/3. How does it increase then?
if we upsize the nmos to size 2, to favour fall delay then both nmos and pmos will have the size 2, this is equivalent to a low skew inverter which is scaled by a factor (k=2), since logical effort is independent of scaling, we are getting the same logical effort, btw even, I feel you are right :)
I think sir told it by mistake, If size(nmos) = 2, Then the reference cmos inverter will have sizes 2(for nmos) and 4(pmos), Hence the logical effort for low skew will be g = 4/6 =2/3.
@@AbhishekSingh-up4rv But overall we are talking about minimum delay. If we upsize the NMOS size to 2, then the input capacitance( i.e. load to the previous gate) is increases from 2C to 4C then the previous gate requires large drive strength to charge the capacitor compared to previous one. That's why he was suppose to consider the NMOS size is 1.
oh! really , then you should go and upscale your level to be able to digest these lectures only then you will realise that this playlist is a real gem for Digital IC design and so is our cool prof.
Sir , Falling Edge will Turn on PMOS right?( Falling edge means input is going from 1 to 0, So 0 will trigger PMOS to get ON). So why you are saying that Falling Edge is determined by the Pull Down Stack.? @ 5:09
falling edge means cap should be connected to gnd and discharge the output cap ( here sir means output falling edge ) , and to connect cap to gnd , nmos stack should be on.
3:28 When we upsize the NMOS to reduce resistance hence fall delay, how is the logical effort increasing. Suppose if we size NMOS from 1 to 2. For gpd, we compare logical effort with an inverter with same drive strength i.e. nmos with size 2 and pmos with size 4(since symmetric cmos inverter). If we calculate gpd - it comes 2/3. How does it increase then?
if we upsize the nmos to size 2, to favour fall delay
then both nmos and pmos will have the size 2,
this is equivalent to a low skew inverter which is scaled by a factor (k=2),
since logical effort is independent of scaling,
we are getting the same logical effort,
btw even, I feel you are right :)
I think sir told it by mistake, If size(nmos) = 2, Then the reference cmos inverter will have sizes 2(for nmos) and 4(pmos), Hence the logical effort for low skew will be g = 4/6 =2/3.
@@AbhishekSingh-up4rv But overall we are talking about minimum delay. If we upsize the NMOS size to 2, then the input capacitance( i.e. load to the previous gate) is increases from 2C to 4C then the previous gate requires large drive strength to charge the capacitor compared to previous one. That's why he was suppose to consider the NMOS size is 1.
It is 3/2
IIT PROFESSORS know how to make easy things look difficult
oh! really , then you should go and upscale your level to be able to digest these lectures only then you will realise that this playlist is a real gem for Digital IC design and so is our cool prof.
why at 21:25 NMOS stack resistance has to be 2R
Since we upsized the gate with "1/2 Factor", Since R scales linearly with Length . So NMOS stack resistance becomes 2R
Sir , Falling Edge will Turn on PMOS right?( Falling edge means input is going from 1 to 0, So 0 will trigger PMOS to get ON).
So why you are saying that Falling Edge is determined by the Pull Down Stack.? @ 5:09
falling edge means cap should be connected to gnd and discharge the output cap ( here sir means output falling edge ) , and to connect cap to gnd , nmos stack should be on.
18.10 how it's 5/3 please help
(5/2)/(3/2) reference inverter changes so we find logical effort accordingly.
@@saheliroychowdhury3253thankyou. Understood😊
I am getting
For Hi skew nand
Gd= 3/2
Gu= 3/4
High skew Nor
Gd= 9/5
GU= 9/10
ANYBODY else??
Check once, you should calculate w.r.t reference inverter ...I think you are calculating w.r.t. same NAND and NOR gate .