Cache Access Example (Part 2)

Discusses how a set of addresses map to two different 2-way set-associative caches and determines the hit rates for each. This is a continuation of • Cache Access Example (... that discussed the same accesses in a direct mapped cache.
NOTE: On the first access to 0x064 for the 2-way associative the LRU bit for Set 1 should be set to 1. This doesn't affect any of the rest of the explanation as the next access also sets the LRU to 1.