Why is it you can explain what takes my teacher about two full weeks of lectures in just two videos under 30 minutes. Thank you so much you're a life saver.
@@DilpreetSingh-eh5kw Yes, I can try to explain here - just had my final today lol. So the LRU stands for Least Recently Used which means we're adopting the eviction policy in which we kick out the address or data or tag or whatever you want to call it in the block that was literally the least recently used. So in this video, Matthew writes out the rows for our little 2 way set associative cache with 2 rows of cache blocks. We can see that up to 0x080, we store our tag in way 0 but when we have our first cache hit with 0x068, we are accessing the same index and thus we look at the first row of our cache. Our LRU bit is set to 1 before our hit because we have been storing our tag in Way 0 and that makes our Way 1 cache the "least recently used." (well we haven't even used it once here yet) so we indicate that by putting 1 there. But after our cache hit with 0x068, we cache our tag into Way 1 and that now makes Way 0 our least recently used, so we just indicate it by putting a 0 there. I think he put the LRU bit block to demonstrate how LRU works but in my exam we didn't have to indicate which block was LRU and stuff. Hope this helps and let me know if you have further questions! :)
Watching both of your videos made everything I know about cache click. Great examples. My final is tomorrow and now I feel that I understand everything about cache which is a quarter of the final. Thank you!
Wow! Thank you for explaining this so well. I'm a hobbyist, so I don't have the benefit of textbooks and courses to work through. Now that I understand the workflows, the next step is describing it in hardware.
i don't understand how I get from 0x070 to the tag of 0000001 and set 1 offset 100000 etc. i.ex.i don't get the translation from the cache access address to the cache address
My first thought is that you are dealing with two different "nomenuclatures", one being hexadecimal and the other being binary. Have you been keeping that it mind?
Hi, although a fully associative cache has the best hit rate, for that particular example, it is worse than 2-way set associative, can you comment on that? Thank you for the nice video.
Right at the beginning of the video, it says 128 B cache. He probably emphasized more in the first video that it was 128 bytes. Matthew Watkins uses the term "ways." I have a textbook which uses the term "lines" and gives "lines" the letter "E" in the equation C = B × E × S Cache_size = Block_size × #_of_lines(or 'ways') × #_of_sets #_of_sets = Cache_size ÷ (Block_size × #_of_lines(or 'ways')) #_of sets = 128 ÷ (32 × 2) #_of sets = 2
You're correct, it should be updated at the first access to 0x064. (Luckily the next access is to the same set and it is updated then, so the end result is not affected.)
Assuming your question is "why do we start with way 0 (and not 1)" the answer is pretty simple, there is no reason why we couldn't have start with way 1 and then went with way 0. I would say though that we went with what is generally consider "conventnion."
Why is it you can explain what takes my teacher about two full weeks of lectures in just two videos under 30 minutes. Thank you so much you're a life saver.
he spent 2 weeks on caches basics ??
you mean shitty teachers?
@@IStMl depends on the syllabus. fully associative, set associative and direct mapped was like half of a topic for me, so it took 1.5-ish weeks
I have finals tomorrow, god bless you
What is the point of V beside the tag, when its value is 1 throughout the process?
And in this case is the value of offset considered? Seems like none of them was used.
i've got my final tomorrow lmao lets gooo
@@chaewoonsong3525 do you understand the use of LSU bit?
@@DilpreetSingh-eh5kw Yes, I can try to explain here - just had my final today lol.
So the LRU stands for Least Recently Used which means we're adopting the eviction policy in which we kick out the address or data or tag or whatever you want to call it in the block that was literally the least recently used.
So in this video, Matthew writes out the rows for our little 2 way set associative cache with 2 rows of cache blocks. We can see that up to 0x080, we store our tag in way 0 but when we have our first cache hit with 0x068, we are accessing the same index and thus we look at the first row of our cache. Our LRU bit is set to 1 before our hit because we have been storing our tag in Way 0 and that makes our Way 1 cache the "least recently used." (well we haven't even used it once here yet) so we indicate that by putting 1 there. But after our cache hit with 0x068, we cache our tag into Way 1 and that now makes Way 0 our least recently used, so we just indicate it by putting a 0 there.
I think he put the LRU bit block to demonstrate how LRU works but in my exam we didn't have to indicate which block was LRU and stuff. Hope this helps and let me know if you have further questions! :)
Exam in 2 days and just found this, I don't think I've ever loved someone over the internet as much as I do right now.
Watching both of your videos made everything I know about cache click. Great examples. My final is tomorrow and now I feel that I understand everything about cache which is a quarter of the final. Thank you!
you're saving our lives , we're taking an exam an hour from now and it's all clear . Thanks
the explanation is really really exhaustive and simple to undestand
5:18 Doesnt the LRU change to 1 because of Hit for last address ??
I didn't know Tom Hanks made videos about instruction pipelining in his free time!
good one
Thank you for both videos. Better than what I got at the university.
Wow! Thank you for explaining this so well. I'm a hobbyist, so I don't have the benefit of textbooks and courses to work through. Now that I understand the workflows, the next step is describing it in hardware.
Final literally in 7 hours!! Thank you
I will have exam question very similar to this and you just saved my life! thanks a lot
Thank you very much! This helped a lot with my university assignment.
thank you so much!! this one helped me and i have exam in few hours!!
You did not update LRU from 0 to 1 for the last address of first stage.
exactly.
i don't understand how I get from 0x070 to the tag of 0000001 and set 1 offset 100000 etc. i.ex.i don't get the translation from the cache access address to the cache address
My first thought is that you are dealing with two different "nomenuclatures", one being hexadecimal and the other being binary. Have you been keeping that it mind?
Hi, although a fully associative cache has the best hit rate, for that particular example, it is worse than 2-way set associative, can you comment on that? Thank you for the nice video.
Thank youu, you're a life savior. :)
ur a life saver
Can you do a 4 way associative example?
Very well explained. Helped me a lot, ty
Thank you, part 1 and 2 have pulled my ass out of the fire.
after the last hit in the 1st time through, why we didnt update the lru as 1 ?
What is the point of V beside the tag, when its value is 1 throughout the process?
And in this case is the value of offset considered? Seems like none of them was used.
What is the size of the cache in the given example? Is it a cache of size 2, or will it be considered a 4 sized cache?
Right at the beginning of the video, it says 128 B cache. He probably emphasized more in the first video that it was 128 bytes.
Matthew Watkins uses the term "ways." I have a textbook which uses the term "lines" and gives "lines" the letter "E" in the equation C = B × E × S
Cache_size = Block_size × #_of_lines(or 'ways') × #_of_sets
#_of_sets = Cache_size ÷ (Block_size × #_of_lines(or 'ways'))
#_of sets = 128 ÷ (32 × 2)
#_of sets = 2
have finals tomorrow thank you!!
On the first time at 0x064 shouldn't you change the LRU to 1?. It doesn't change anything i am just asking to see if i got it right
You're correct, it should be updated at the first access to 0x064. (Luckily the next access is to the same set and it is updated then, so the end result is not affected.)
What is the point of V beside the tag, when its value is 1 throughout the process?
And in this case is the value of offset considered? Seems like none of them was used.
u a real one
Is there a transcript of the video?
this saved my life
ty
god bless you , this one helped me a lot !!!
why do we go with way 0 first?
Assuming your question is "why do we start with way 0 (and not 1)" the answer is pretty simple, there is no reason why we couldn't have start with way 1 and then went with way 0. I would say though that we went with what is generally consider "conventnion."
another good one , thanks a lot!!
great stuff 👌👌
Thank you! Very good video
it's helpful
thank you!
if tag has matched but valid bit is 0, then will it be a hit or miss?
It is impossible? When valid bit is 0, the cache line is not filled with anything.
Legend!
thank you so much
You are an angel lol, saved my ass
great!!!!
unluckyly you dont say if is compulsory, conflict or capacity, too much easy in this way
you saved my ass
WOW WOW Nice vido
No, sorry.
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