Is your question, is it "least recently useder" or "most recetly used?" If so, I don't belieft that plays a roll at the level of abstrication this problem is dealing with.
@@matthewwatkins88 yes i just saw your other video about 2-way associative and it helped a lot! thank you! one more question, though, if the offset is log(number of bytes in the set) then doesnt the set contain 2 words (double the amount of bytes) which means it becomes log(2*32)=6 or does it only depend on the block size I've seen the words block and set used interchangeably sometimes so this concept is pretty confusing for me Hope my question is clear though
so to find the CPI, we count numbers of cycles from the WB of the 1st instruction (which happens at cycle 5) until the end... so until WB of j loop, which happens at cycle 17... meaning that's 13 cycles, so why does he say 14? are we counting the nop in there to make it 14?
Assuming I understand your question correctly, the algorthm, in the first case (IE, the first option, which is what is discused in this video) does a direct-mapped set of operations. The follow-on video after this one then condifers two other options and briefly discusses the trade-offs between the three.
When you say "RISC" do you mean actual RISC? If so, actual RISC code is equavelent to what is shown. If you are refering to the Mips code, then yes, real Mips code would change the performance, but it doen't necesarily destroy it.
Extremely helpful. Seems very simple and has not changed for so many years but still i get confused time to time so review of the video was great refresher.
Can you explain how you arrived at that statement? This figure has 30 gates. A standard ripple carry would take 30 stages. The figure in this video has 10+3 (=13) stages for the max delay.
Assuming your question is "why do we start with way 0 (and not 1)" the answer is pretty simple, there is no reason why we couldn't have start with way 1 and then went with way 0. I would say though that we went with what is generally consider "conventnion."
Off the top of my head, I'm not sure what you are refering to by "CNF method." If you can expand a little, I likely would be able to respond more helpfully.
At first you say that Neither branch is taken but at the end the last one you tell us that again Neither of the branch is taken. I am confused can you help me understand if i get something wrong?
i don't understand how I get from 0x070 to the tag of 0000001 and set 1 offset 100000 etc. i.ex.i don't get the translation from the cache access address to the cache address
My first thought is that you are dealing with two different "nomenuclatures", one being hexadecimal and the other being binary. Have you been keeping that it mind?
I have a question. What if the addresses in memory are not all uniform bit size. Each of your addresses in the example are 12 bit. But what if they differ, such as between 12 - 16 bits? Will the process you are using here work on addresses of varying bits? Such as 0x408ed4, 0x10019d94, 408ed8...
Assuning you are refering to immediate values (bit positation 15-0 for the immediate values portion) they are all 16 bits. It may only show a smaller number if the higher order bits are all zero. As a further extendion, in MIPS, all addresses are 32 bits (with immediate values of 16 bits). Does that address your question?
hocam hiçbir şey anlamadım cidden
Is this based on LRU or MRU replacement policy? How do they differ?
Is your question, is it "least recently useder" or "most recetly used?" If so, I don't belieft that plays a roll at the level of abstrication this problem is dealing with.
@@matthewwatkins88 yes i just saw your other video about 2-way associative and it helped a lot! thank you! one more question, though, if the offset is log(number of bytes in the set) then doesnt the set contain 2 words (double the amount of bytes) which means it becomes log(2*32)=6 or does it only depend on the block size I've seen the words block and set used interchangeably sometimes so this concept is pretty confusing for me Hope my question is clear though
@@LAVENDER-OG What you typed is in the "wrong" direction. Each word gives you 4 bytes, NOT 4 words gives you 1 byte. Does that help/solve the problem?
so to find the CPI, we count numbers of cycles from the WB of the 1st instruction (which happens at cycle 5) until the end... so until WB of j loop, which happens at cycle 17... meaning that's 13 cycles, so why does he say 14? are we counting the nop in there to make it 14?
Yes, if there is a NOP, we need to acount for that and includer that in the caluation of the CPI.
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Assuming I understand your question correctly, the algorthm, in the first case (IE, the first option, which is what is discused in this video) does a direct-mapped set of operations. The follow-on video after this one then condifers two other options and briefly discusses the trade-offs between the three.
danke schon
You are telling me it was this simple?
many thanks sir
Oh come on throw those branch delays in and show how inefficient RISC code is.
When you say "RISC" do you mean actual RISC? If so, actual RISC code is equavelent to what is shown. If you are refering to the Mips code, then yes, real Mips code would change the performance, but it doen't necesarily destroy it.
7 years later, and still useful! Thanks much for the introduction to Xilinx DSP.
thank you!
Extremely helpful. Seems very simple and has not changed for so many years but still i get confused time to time so review of the video was great refresher.
So helpful!!!
Thank you so much!!
thank you tony stark
If we dont have the last line, what the pipeline will be? Can we begin the IF of the first loop line directly in circle 14?
The last line, as I interpret it anyway, is never executed, so removing it really wouldn't change anything.
@@matthewwatkins88 I see. Thank you very much!
this seems longer in terms of prop delay than just using ripple carry?
Can you explain how you arrived at that statement? This figure has 30 gates. A standard ripple carry would take 30 stages. The figure in this video has 10+3 (=13) stages for the max delay.
This is so cool
Thanks for helping out!
Isn't it 13 instructions in the loop? (including 5 to 17)....or did he include the 18th cycle?
It does say it takes 13 (17) cycles to complete the loop (so I'm unsure about the issue)
@@matthewwatkins88 yup just realized...Great work!!
Excellent video. Than you so much.
GREAT VIDEO THANK YOU helped me with my lab 3 project :)
why do we go with way 0 first?
Assuming your question is "why do we start with way 0 (and not 1)" the answer is pretty simple, there is no reason why we couldn't have start with way 1 and then went with way 0. I would say though that we went with what is generally consider "conventnion."
Would this grouping method work for the CNF method?
Off the top of my head, I'm not sure what you are refering to by "CNF method." If you can expand a little, I likely would be able to respond more helpfully.
Still helping me in 2024 - big thanks!
true
Thank you so much! This tutorial was a lifesaver.
(Y)
one of the best explanations
You guys rock! This video answers ‘The abstract’ 😍
GOD BLESS YOU FOR THIS!!!💪
nice
I think in the third case you meant first branch (beq $t0,$0, end) is taken only
I'll stop my head, I would agree with you.
Great video, much better explained than my professor.
He didn’t even explain he just told u what to do 😤
At first you say that Neither branch is taken but at the end the last one you tell us that again Neither of the branch is taken. I am confused can you help me understand if i get something wrong?
This video shows all three cases. So you will learn about all three options by watching this video.
@@matthewwatkins88 When the exercise says that the branch is followed i should think that the branch is taken or not taken?
At one instant in time the branch is either taken or not taken. But the video shows both options so you will learn about both cases from the video.
@@matthewwatkins88 Thanks a lot.
Hey, thank you very much for you great example, I was trying to remember logic circuits, and that was so helpful
thank you for saving my life
i don't understand how I get from 0x070 to the tag of 0000001 and set 1 offset 100000 etc. i.ex.i don't get the translation from the cache access address to the cache address
My first thought is that you are dealing with two different "nomenuclatures", one being hexadecimal and the other being binary. Have you been keeping that it mind?
❤😊
Very good content!!!! Thank you very much!
ur a life saver
Please speak in hindi.
I have a question. What if the addresses in memory are not all uniform bit size. Each of your addresses in the example are 12 bit. But what if they differ, such as between 12 - 16 bits? Will the process you are using here work on addresses of varying bits? Such as 0x408ed4, 0x10019d94, 408ed8...
Assuning you are refering to immediate values (bit positation 15-0 for the immediate values portion) they are all 16 bits. It may only show a smaller number if the higher order bits are all zero. As a further extendion, in MIPS, all addresses are 32 bits (with immediate values of 16 bits). Does that address your question?
@@matthewwatkins88 yes ok thank you very much for your answer!
What happens when blocking and nonblocking assignments are intermixed?
In what way would mixing blocking and non-blocking assignments cause issues?
👍👍👍👍👍
Thank you for both videos. Better than what I got at the university.
Teşekkürler verdiğiniz bilgi için.
goat no one explains it better and got a final tomorrow wish me luck
Absolutely amazing and helpful!
great example, thank you!
5:18 Doesnt the LRU change to 1 because of Hit for last address ??
Save me from the poor lecture notes but advanced question sheet