If you don't just happen to have DSP experience, or extra time, a hardware tone detector is a good approach. The DSP approach (the ATMEGA, with its single cycle multiplier, is fine) does allow you to recover a specific harmonic regardless of varying line frequency. But, it's far more complicated. The approach that requires the least math is probably to use a zero crossing detector on input capture, and do a software phase locked loop so that the timer fires at 192x line frequency, or 8 times per 1440Hz period. Have the timer trigger the ADC using hardware trigger, and integrate the ADC over 960 samples in a length-8 array. Finally, multiply each element by a sine with a period of 8 samples and take the sum. Call that I. Repeat that, but with a cosine instead, call that Q (you will want length-8 sin/cos table). Finally Pythagoras A²=I²+Q² gives the amplitude, and here you can happily avoid doing square root. This filter will have side lobes due to the flat-impulse integration, and 6Hz -3dB bandwidth due to the 83ms integration time. We can of course do better, by summing I,Q more often and running them through a FIR filter, but, see the very first statement..
Yeah once I get around to making another model I'll use DSP, I just need to get more used to it and use a faster processor for it to be useful. I was using a basic Goertzel algorithm implementation which I'm not really sure how similar your example is, but I'll give it a shot.
@@KJ7BZC Goertzel is the hard way, and you only want to detect one frequency, not many. What I am suggesting here is an IQ downconverter (if this was in the analog domain, it would be two mixers fed with 0 and 90deg. from a 1440Hz local oscillator, followed by low pass filters. It is also called a zero intermediate frequency receiver), a complex (as in number) low pass filter, and an amplitude comparator. But, it's folded up a bit differently to reduce cpu requirements. To run it, you need ~12000* 16-bit read-add-write operations and ~200* 32-bit multiplications per second; Double the number of multiplications if a FIR filter is used on the output. It behaves closel enough to the full-fat FIR implementation that the difference is negligible, but you can do it on pretty much any microcontroller with an ADC. (*My example was targeted at ATMega's ADC, and 8 samples per cycle, making an external anti-aliasing filter easier. You can run with half the samplerate and 4 samples per cycle for half the cpu load).
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Nice work man!
If you don't just happen to have DSP experience, or extra time, a hardware tone detector is a good approach. The DSP approach (the ATMEGA, with its single cycle multiplier, is fine) does allow you to recover a specific harmonic regardless of varying line frequency.
But, it's far more complicated.
The approach that requires the least math is probably to use a zero crossing detector on input capture, and do a software phase locked loop so that the timer fires at 192x line frequency, or 8 times per 1440Hz period. Have the timer trigger the ADC using hardware trigger, and integrate the ADC over 960 samples in a length-8 array. Finally, multiply each element by a sine with a period of 8 samples and take the sum. Call that I. Repeat that, but with a cosine instead, call that Q (you will want length-8 sin/cos table). Finally Pythagoras A²=I²+Q² gives the amplitude, and here you can happily avoid doing square root. This filter will have side lobes due to the flat-impulse integration, and 6Hz -3dB bandwidth due to the 83ms integration time. We can of course do better, by summing I,Q more often and running them through a FIR filter, but, see the very first statement..
Yeah once I get around to making another model I'll use DSP, I just need to get more used to it and use a faster processor for it to be useful. I was using a basic Goertzel algorithm implementation which I'm not really sure how similar your example is, but I'll give it a shot.
@@KJ7BZC Goertzel is the hard way, and you only want to detect one frequency, not many. What I am suggesting here is an IQ downconverter (if this was in the analog domain, it would be two mixers fed with 0 and 90deg. from a 1440Hz local oscillator, followed by low pass filters. It is also called a zero intermediate frequency receiver), a complex (as in number) low pass filter, and an amplitude comparator. But, it's folded up a bit differently to reduce cpu requirements. To run it, you need ~12000* 16-bit read-add-write operations and ~200* 32-bit multiplications per second; Double the number of multiplications if a FIR filter is used on the output. It behaves closel enough to the full-fat FIR implementation that the difference is negligible, but you can do it on pretty much any microcontroller with an ADC. (*My example was targeted at ATMega's ADC, and 8 samples per cycle, making an external anti-aliasing filter easier. You can run with half the samplerate and 4 samples per cycle for half the cpu load).
@@KJ7BZC Cool man, can i know how you make it? Have you open sourced it on any forum?
cool!
Are you just casually sitting on a piece of wood floating in the air or something?
Yes
@@KJ7BZC hopefully you don’t fall down and break your legs lol