Mam,in c mos nandgate,what is the use of connecting two n mosfets rather than connecting it directly to the ground as that of p mos nandgate.i mean that the use of those two nmosfets has no effect.i.e the output is dependent on pmosfets.
For a NAND gate, output is 0 if both inputs are high, that means pulldown network should conduct when both inputs are 1.This happens if and only if NMOS transistors are in series. If any one of the inputs is 0, output must be 1. That means PMOS should conduct if any one of the two inputs is 0. That means PMIS are in shunt - just opposite to the NMOS connection
Check out Digital Electronics courses at: bit.ly/3aIM1ur
Use coupon "RUclips12" to get FLAT 12% OFF
You've explained every logic circuits perfectly.
Heartily grateful to you ma'am.
maam you teach me in very easy way . i watch many video but i understood only through your lecture .
the way u discussed was very nice...understood the entire thing clearly...keep making videos...
how i get this full play list..????🙄🙄🙄
ur a great teacher each students dream to have..just by one explanation urs we will understand everything.. 🙏🙏🙏..great guru ur..
This channel is goated. You are the reason I am passing my EE classes in undergrad
Thank you for making this so easy to understand!! You saved a lot of my time :)
Thank you ma'am for the simple and good way explanation
You answering my questions well, thanks
Oooo thank you so much dear mam❤❤i have seeing this before two days of exams ....n i got it 😍😍❤❤once again thank u❤
Great explaination. Thank you mam.
thank you madam😇blessings be on u
Very nice explanation mam..
Great
👍👌👍👌👍👌👍👌👍👌
Mam,in c mos nandgate,what is the use of connecting two n mosfets rather than connecting it directly to the ground as that of p mos nandgate.i mean that the use of those two nmosfets has no effect.i.e the output is dependent on pmosfets.
Sister u explanation is gud but if u provide captions it is helpful fr us fr writing notes hope u consider it
I had no problem understanding her to be honest
Ma'am please make a video on 3 inputs NAND AND NOR GATES BY CMOS
Our sir sent us back to learn this and come for viva or else he will roast us..after watching your video we got 10/10!!! Superb ma'am ❤️😀😀😀
Muchas Gracias mi maestra para ayudándome . Que significa mucho para mí
Nice explanation Mam thank u very much
thanks for this wonderfull explanation
Great explanation!
Nice presentation
Clearly explanation
Thank u ❤️❤️
Yes really nice video and nice explanation
Thank u so much...
brilliant video ma'am. thank you so much
Yes, really nice video, isn't it?
Amazing Video, Thank you
Easy to understand explanation
Beautiful..
best explication ever....thank u !
Yes, really nice video....
This video u not put it in playlists,sis
Mam what is CMOS two four input NAND gate
How u drawn the diagram mam
Your really great mam and thanks mam
ótima explicação, obrigado!
Can you please repeat in English.....
Thanks
woow beauty lady your tutor is very nice!! Thank you very much!
Really nice video, isn't it?
Ty madam for explanation
Thank u😊
Will u teach NA(network analysis)..
Excellent Explination mam
thanks
Thanks so much mam
Powerful lady..
Thank you mam
Mam naku eca link pentundi
thanks you
good and clear explanation.. Thank you mam
Yes really nice videos
What a explanation
Your explanation good madam
Very good explanation
Very nice tutorial
Thank u mam
Thanks for your class mam
thanks mate
Yet we are where we begin...
What's piety and impiety?
Thank you Ms
Easily understandable.....
Nice video....
Can you Draw a NAND gate using only 3 transistors?
Mam your teach is very good & I have one dout did you explain the ECL in next video
Shall I make video on ECL?
mam you explain very perfect
Yes really nice explanation....
is the connection to ground is necessary for a 0 o/p? ie, if the o/p is neither connected to Vdd nor ground, will it give a 0 o/p?
No, output will be at high impedance state. In this case output is either 0 or 1
Thank you madam
MANY MANY THANKS
teams.microsoft.com/l/message/19:c5b22403fb4b48b98884216ddc773112@thread.tacv2/1598413137848?groupId=112929d5-7a03-4aab-897b-8cbc9e4e254f
OP EXPLANATION👌👌👍
thanks mam
TQ mam 👍
Op explanation🔥
Nice explanation madam
thanks maam
Nice ma'am
Nice
Tanks mem
Tq madam 😘
Ma'am please make a tutorial on SRAM
Shall I make a video on SRAM?
if we will invert positions of NMOS & PMOS so it will become AND gate? Please help, thanks
I also notice this..
No, if you use an inverter at the output it will work as an and gate.
Super madam
Thank you so much
Nice video right....
Madam can u provide notes
The way you explained is good but why cant you draw the circuit while explaining rather drawing it at first
valo hoeche
2-input AND&OR gate explain
🔥🔥🔥🔥❤️
Subtiles needed mam
how can I draw this structure with the help of nand truth table....
Realise the circuit using NMOS, then take complement of that network, means if NMOS is a shunt network, PMOS becomes series network and vice versa
For a NAND gate, output is 0 if both inputs are high, that means pulldown network should conduct when both inputs are 1.This happens if and only if NMOS transistors are in series. If any one of the inputs is 0, output must be 1. That means PMOS should conduct if any one of the two inputs is 0. That means PMIS are in shunt - just opposite to the NMOS connection
2 input nand gate using cmos Ela construct chestaroo cheppandi
Can you repeat in english?
can u share and gate and or gate by using cmos
I will make a video on and and or gate. Shall I. ? It is very easy, connect a not gate at the output of NAND and nor gate?
Mem hindi ne samja dijiye
Circute😅😅😅😅😀😀😁😁🤣😂
NOT HELPFUL
RIP English
thank u very very much mam
Thank u so much.
thanks mam
Nice
Thank you mam
Really nice video, isn't it?
Nice