Half Adder | Full Adder| CST203/ECT203/EET206 | Logic System Design / Digital Electronics | KTU

Syllabus Common to :
APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY (KTU)
(REGULATION 2019)
1)CST203 Logic System Design ( COMPUTER SCIENCE ENGINEERING)
2)ECT203 Logic Circuit Design (ELECTRONICS AND COMMUNICATION ENGINEERING)
3)EET206 Digital Electronics ( ELECTRICAL AND ELECTRONICS ENGINEERING)
4)ITT203 Logic System Design (INFORMATION TECHNOLOGY)
5)EBT205 Logic Circuit and Design (BIOMEDICAL ENGINEERING)
6)ICT203 Design of Logic Circuits (INSTRUMENTATION AND CONTROL ENGINEERING)
7)ECT203 Logic Circuit Design (APPLIED ELECTRONICS ENGINEERING)
(REGULATION 2015)
1)CS203 Switching Theory and Logic Design (COMPUTER SCIENCE ENGINEERING)
2)IT201 Logic System Design (INFORMATION TECHNOLOGY)
3)EC207 Logic Circuit Design (ELECTRONICS AND COMMUNICATION ENGINEERING)
4)EE204 Digital Electronics and Logic Design (ELECTRICAL AND ELECTRONICS ENGINEERING)
5)EC207 Logic Circuit Design (APPLIED ELECTRONICS ENGINEERING AND INSTRUMENTATION)
6)IC207 Design of Logic Circuit (BIOMEDICAL ENGINEERING)
COCHIN UNIVERSITY OF SCIENCE AND TECHNOLOGY
1) Master of Computer Applications (MCA)
20-381-0103 Digital Electronics and Computer Organization
2)EC-15-1304 Digital Electronics (BTECH ELECTRONICS AND COMMUNICATION ENGINEERING)
3)CS-14-1302 & 19-202-0302 Logic Design (BTECH COMPUTER SCIENCE ENGINEERING)
4)EE-15-1405 Digital Electronics ( ELECTRICAL AND ELECTRONICS ENGINEERING)
KERALA POLYTECHNIC DIPLOMA (SITTR KERALA)
1) 3042 DIGITAL ELECTRONICS ( DIPLOMA ELECTRONICS ENGINEERING)
2) 3042 DIGITAL ELECTRONICS ( DIPLOMA ELECTRONICS AND COMMUNICATION ENGINEERING)
ANNA UNIVERSITY ( REGULATION 2017)
1)EC8392 Digital Electronics (BE ELECTRONICS AND COMMUNICATION ENGINEERING)
2)EE8391 Digital Logic Circuits (BE ELECTRICAL AND ELECTRONICS ENGINEERING)
3)EE8351 Digital Logic Circuit (BE ELECTRONICS AND INSTRUMENTATION ENGINEERING)
4)CS8351 Digital Principles and System Design (BE COMPUTER SCIENCE ENGINEERING)
5)CS8351 Digital Principles and System Design (BE INFORMATION AND TECHNOLOGY)

[@abhijithanandn6288]

Great sir⚡️

[@anaminfathima958]

Thank you so much sir.Your videos were very helpful.

[@anandmohan5538]

Very helpful

[@mohammedsafvan6344]

exceptional.

[@muhammedalthaf1910]

Pwolii maah n 🎉🎉

[@Bensio010]

sir in example 2 ,whether y=C ^- + ( A ^- . B ^-) is the boolean expression,

[@battleragecoc9411]

In the Example 2, they haven't mentioned the number of variables. In that case, what am i supposed to do? take 3 by default? or 4?

[@ShastraTechnicalInstitute]

that's our choice !!!! Ethu input venamenkilum edukkam ! By default 3 edukkam

[@gokulharidas2931]

@@ShastraTechnicalInstitute eniku kittuyath a-b-+a-c-+b-c- ( "-" utheshichath dash ennu anney😁)

[@_geatt]

@@gokulharidas2931 enikkum same aa kittiyath

[@yadhunandang5542]

@@gokulharidas2931 correct arikkum enikkum atha kittiye

[@abhijithjithu8782]

Thank u sir

[@ajnaskp386]

👍👍👍

[@Apxc.]

Sir ,XOR gate nee eganne NAND or NOR gate akan mattum, sometimes draw the logic diagram using universal logic ennu chothichalo

[@abhishekkannath]

👍

[@georgejosephp5520]

Thank you

[@suhanasalim981]

Thanks sir

[@Aj_An_]

Welcome dear

[@micdrip6934]

Xam n pass aavan vendi important qns idavoo sir

[@Aj_An_]

Ok

[@aishhk8252]

Thanku sir 😌

[@ShastraTechnicalInstitute]

Always Welcome..

[@sureshmaahi5840]

Eg 2 il sop aano cheyyande

[@mytech2067]

In example 2 sop or pos?pls answer anyone?

[@adnanyousuf5014]

🙋

[@kingsha1841]

Eg:2 ans sir

[@Aj_An_]

Hmm

[@minimalrandom]

​@@Aj_An_xam 🫂

[@donalsiby6920]

Ee video el ollaa PPT kettuvo.

[@muhammedfarsad4669]

9:59 am: Afternoon exm..clsin onnum mansilyilla ippo ellm clear aayi

[@at_h_i_r_a]

Sir plss.. Add synchronous and asynchronous counters ASAP

[@ShastraTechnicalInstitute]

Uploaded

[@sreekumarpm3497]

Eg 2 answer ntha kittane

[@shaunbiju5875]

Eg 2 ill sop or pos

[@aliyasalim5559]

sir example 2 il ethra input m outputm undenn engana kand pidikunnen onn paranj tharavo?

[@ShastraTechnicalInstitute]

Single Output...
3 Inputs

[@fathimasaliha6710]

How do we draw the logic diagram of example 2

[@ShastraTechnicalInstitute]

The same step should be followed as discussed in example 1

[@amrutheshvijayan6265]

Half adder using Nand gate and Nor gate vendeee

[@lucyabrahamthomas8379]

Eg2 boolean expression Y=AbarCbar+BbarCbar+AbarBbar ano?

[@anonymous-wy1wu]

Enikkum ee answer aanu kittiye...

[@meghabenny6341]

Me too same answer

[@Anjali-dn3hu]

Ith pos aavumbo middleil aley + vera?

[@wizardfire555]

Yes

[@roshan1424]

example 2 home questionu ethra output undd

[@tuneboyz5634]

kunjaava Roshan

[@jithinjoy4806]

Sir question ചോദിക്കുന്നത് sop aano pos aano ennu engane manasilaakkaam pattum?

[@femi2k2]

Same doubt🥲

[@soosanfrancis7755]

full adder inte sum inte boolean equation corect ano , enikk kittunulla athu

[@ZEUSGaminG-mi3nt]

Ennikum 😖

[@ZEUSGaminG-mi3nt]

Enniku carry equation manasil aii illa

[@aliyasalim5559]

sir pls add the answer of example 2

[@roshan_a_]

Answer inganeyano kittanathu:
A'B'+B'C'+A'C'

[@Bensio010]

@@roshan_a_ alla bro,bro group chytathe thetti poyathane.

[@jefinjose9159]

Implement by universal gate
Class edamo

[@circuitsanalytica4348]

In my channel, you can find some examples....

[@ashikajan5088]

sir sound illa sir

[@ShastraTechnicalInstitute]

Audible alle

[@ashikajan5088]

No sir

[@hrizhi]

Sir Half adder and full adder using NOR and NAND important aano? atho ath skip cheyaano?

[@ShastraTechnicalInstitute]

Important aanu

[@john_wick_45]

@@ShastraTechnicalInstitute video onnu upload cheyavo

[@mayamaya-hb2dj]

@@john_wick_45 using nand vdio upload cheydhitille..!?

[@muhammedaflah7920]

Pdf notes ndo

[@athulya7485]

sir POS nthan upayogikkathey
eg1

[@lucyabrahamthomas8379]

Eg 1 ilum 2ilum sop alle cheyyande?

[@circuitsanalytica4348]

SOP and POS are selected based on the expression. If expression is ABC + A'BC' then it is SUM OF TWO PRODUCT TERMS ABC AND A'BC', So SOP. If the expression is PRODUCT OF SEVERAL SUM TERMS like (A+B+C)(A'+B'C), then POS

[@leviackerman3935]

@@circuitsanalytica4348 yeah, but in example 1 in the question expression is not given [(ABC) +(ABC) nor (A+B+C) (A+B+C)]. Then how can we understand wheather it is POS or SOP ?

[@nishlasaleem856]

@@leviackerman3935truth table l output 1 akumpol sop , 0 akumbol pos

[@mushrifasherinc7456]

EET 206 ITH PADICHA MATHIYOO

[@ignite6587]

Sir all module note undo pls🙂

[@ShastraTechnicalInstitute]

Notes are under preparation !! Partial module notes available... mail me [e-mail]

[@ignite6587]

@@aswathipj1187 yes

[@ignite6587]

@@aswathipj1187 i have only the links

[@ignite6587]

@@aswathipj1187 u r mail id

[@sanajeron6902]

Sir labinta experiments onn discuss cheyyavo

[@ShastraTechnicalInstitute]

Athu kure undu parayan !! Ini time undaavo nnu ariyilla

[@anuk2629]

bsc student

[@niranjan8036]

Eg 2 answer evide?😊

[@Aj_An_]

Home work

[@AashTecTheEngineersChannel]

Sir eg 2 ethra output ondenn engane manassilaayi

[@AashTecTheEngineersChannel]

Sorry input ethra undenn engana manassilaayi

[@ShastraTechnicalInstitute]

U can choose any one example.. 3 input.. 4 input etc

[@exodusvampire6080]

Sir, can you provide the notes.

[@ShastraTechnicalInstitute]

Full Module Notes are under Preparation !!

[@sreejagkgk5752]

Sir note tharamo

[@amalkrisna]

thankyou sir

[@salmah7675]

👍