Asynchronous Counter | Up Down and Modulo Counter | CST203 ECT203 EET206 | Logic System Design KTU
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- Опубликовано: 2 дек 2020
- Syllabus Common to :
APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY (KTU)
(REGULATION 2019)
1)CST203 Logic System Design ( COMPUTER SCIENCE ENGINEERING)
2)ECT203 Logic Circuit Design (ELECTRONICS AND COMMUNICATION ENGINEERING)
3)EET206 Digital Electronics ( ELECTRICAL AND ELECTRONICS ENGINEERING)
4)ITT203 Logic System Design (INFORMATION TECHNOLOGY)
5)EBT205 Logic Circuit and Design (BIOMEDICAL ENGINEERING)
6)ICT203 Design of Logic Circuits (INSTRUMENTATION AND CONTROL ENGINEERING)
7)ECT203 Logic Circuit Design (APPLIED ELECTRONICS ENGINEERING)
(REGULATION 2015)
1)CS203 Switching Theory and Logic Design (COMPUTER SCIENCE ENGINEERING)
2)IT201 Logic System Design (INFORMATION TECHNOLOGY)
3)EC207 Logic Circuit Design (ELECTRONICS AND COMMUNICATION ENGINEERING)
4)EE204 Digital Electronics and Logic Design (ELECTRICAL AND ELECTRONICS ENGINEERING)
5)EC207 Logic Circuit Design (APPLIED ELECTRONICS ENGINEERING AND INSTRUMENTATION)
6)IC207 Design of Logic Circuit (BIOMEDICAL ENGINEERING)
COCHIN UNIVERSITY OF SCIENCE AND TECHNOLOGY
1) Master of Computer Applications (MCA)
20-381-0103 Digital Electronics and Computer Organization
2)EC-15-1304 Digital Electronics (BTECH ELECTRONICS AND COMMUNICATION ENGINEERING)
3)CS-14-1302 & 19-202-0302 Logic Design (BTECH COMPUTER SCIENCE ENGINEERING)
4)EE-15-1405 Digital Electronics ( ELECTRICAL AND ELECTRONICS ENGINEERING)
KERALA POLYTECHNIC DIPLOMA (SITTR KERALA)
1) 3042 DIGITAL ELECTRONICS ( DIPLOMA ELECTRONICS ENGINEERING)
2) 3042 DIGITAL ELECTRONICS ( DIPLOMA ELECTRONICS AND COMMUNICATION ENGINEERING)
ANNA UNIVERSITY ( REGULATION 2017)
1)EC8392 Digital Electronics (BE ELECTRONICS AND COMMUNICATION ENGINEERING)
2)EE8391 Digital Logic Circuits (BE ELECTRICAL AND ELECTRONICS ENGINEERING)
3)EE8351 Digital Logic Circuit (BE ELECTRONICS AND INSTRUMENTATION ENGINEERING)
4)CS8351 Digital Principles and System Design (BE COMPUTER SCIENCE ENGINEERING)
5)CS8351 Digital Principles and System Design (BE INFORMATION AND TECHNOLOGY)
Way Better than my college class❤️💯👏
💯💯💯💯💯
Which college are youfrom
@@adonis9568 ah yes a fellow last minute learner. How much more to go my good man?
@@tomatosauce3325 😁 ninak ethrundenn para
@@adonis9568 I've been behind this from the morning. I haven't completed mod 4 and everything after that yet ;-; but 70 marks pore, there's hope haha.
I wish I found this sir's playlist earlier :p you?
Sr... Ur presentation..... Super........ I got all concepts regarding this topic.....god bless u
really helpful sir. very good class
Thnkuuu soo much sir. This is my seminar portion
No words to express ☺️awesome 🥰
Sir super class. Really like it
remainder...
examinu mumbu revision vendi kanunnavar..
1.75 speed try cheyuu...
trust me..it worked!!!
Thank's🤩
ivade 2X pora...apazha🥲
@@gourimmenon2726 yaa
@@gourimmenon2726 avastha anu
I tried 2.6 X speed using video speed controller its effective than 2X
Very good class sir..
veru very very very very very helpfull
Very helpful..
Thankyou for these useful lectures.
@21:32 why there is a slight diffference for the beggining of qa,qb,qc
sir pls reply
Thank you sir
😌Thanku sir
Always Welcome.. Keep watching 😍🥰
Very good class sir
BCD Counter Logic diagram is False. Bcoz If we want to get 1,1 then we need to Connect to QA and QC to the NAND gate
sir 22.50 isnt it down counter so we shud use qa bar qb bar ?
❤️🤝
CST203 LSDku refer cheyan oru nalla text suggest cheyamo pls ?
Kurachu Kodi problems okke ulla valla text ?
Yes that'd be a great help
Fundamentals of Digital Circuits by Anand Kumar
Nice class 👍
sir 29:29 NAND lekk 1,1 pass cheythal out 0 alle. 0 varumbo aano clr set aavunnath
Clr 0 activate avum
sir ee timing diagram varakkunnathu manasilavunilla..
njan truth table anusarichu varakkunathum sir varakkunathum different annu..
sir kindly help me.
UP DOWN ripple counter engane design cheyya?
Super class
Sir mod 10 down counteril timing diagram and reset circuit engane varakum..timing diagram engane 9 inu start cheyum normally 15 or 0 oke ale start ayt varene.?
0 t0 9 vare ulla timing diagram varakkanam.. 9 kazhinjaal again 0
QD QC QB QA Order il varakkanam
Sir 3 bit asynchronous up counteril 0-7 vare varkende timing diagramil presentationil kandilla adha choiche
sir examine design 4bit ripple cunter chodichal ithe upcounting ano allekil downcounting ano cheyandathe
Sir ithil , 21:32 il clock pulse varakkumbol 0 ilninnum alle start cheyyande? truth table appozhalle corresponding aavane?
sir @21:32
aah timing diagram thettalle sir...
clock 1 akumbo QA 1 alle avende
but timing diagram ill 0 alle varachekunne..
athupole thanne bakki ellam changes varille
@Unni ok.
athu pole ee video ill ulla matte timing diagramilum mattam ille
@Unni yes..athum thettalle timing diagram..
Sir Can You Please Upload Registers
Yes Yes Uploaded
@22:34 timing diagram of 4 bit down counter varumbo timing diagram clear alla.
Qa,Qb,Qc,Qd varachal timing diagram of 4 bit up counter alle
Sir athonn explain cheyth tharanam pls
Sir njan mail ayachind onnu nokamo sir,?!
Sir notes pls nale exam ahnn