RISC-V Logisim Immediate Generator
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- Опубликовано: 24 май 2024
- Learn about the RISC-V instruction set architecture by building hardware. In this video, I use Logisim to build the Immediate Generator that will eventually be incorporated into an RV32I CPU that can be synthesized on to an FPGA.
Immediates touch on many classes of instructions and are fundamental to understanding the RISC-V philosophy.
There are a number of resources that I recommend you study as you go on this journey with me:
RISC-V Reference Card: www.cl.cam.ac.uk/teaching/161...
Design of the RISC-V Instruction Set Architecture: digitalassets.lib.berkeley.ed...
Great Ideas in Computer Architecture (week 2 and 4): inst.eecs.berkeley.edu/~cs61c...
RISC-V Specification: riscv.org/wp-content/uploads/...
Other helpful resources:
Online RISC-V assembler: riscvasm.lucasteske.dev
Logisim Evolution: github.com/logisim-evolution/...
this seems like i will come back to it one day.
pretty cool video! i really hope you make more. ❤
Thank you, I will
Interesting but I dont understand whats going on. Very specific usage. This is for programming basically an OS or interface that you can communicate with? Definately interesting, just a little too high level i think for most viewers.
Like for example, what are we doinfgwirh thw bit values ect. And how are we using this?
I am building modules step by step, that will be combined into a design, which will implement a RISC-V system on a chip, in Logisim. The immediate generator acts upon RISC-V immediate instruction types, which contain hard-coded values within the instruction. Those immediate values are then needed by other modules (such as the ALU). Perhaps I did not add enough context at the beginning of the video. Have you have seen other videos in the series? I am about to deploy content on control logic, which pulls these modules together. Thanks for the question.
its Kinda hard to comprehend sir
Have a specific question that I can clear up?