171N. Circuit compensation techniques, one- and two-stage op-amp, Miller compensation
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- Опубликовано: 18 дек 2024
- Analog Circuit Design (New 2019)
Professor Ali Hajimiri
California Institute of Technology (Caltech)
chic.caltech.ed...
© Copyright, Ali Hajimiri
My final is in 12 hours and now I finally understand miller compensation. Thank you sir 🙏
I just wanted to ask one question. How do you simplify and understand the things which are not written in a book so easily? I have observed that u are able to solve the doubts(good questions) of ur students so easily. Prof can you please tell me how do you approach a particular doubt,problem or a new topic? Bcoz it takes me a hell lot of time to understand one particular topic clearly(even after reading books and watching videos). We love u sir!!
I guess the key is to all of it is to constantly think about it and try it so many different ways. The more you keep something on your mind, the deeper your understanding becomes. Hope this helps and thank you for your kindness.
@@AliHajimiriChannel Thank you☺
Prof. @@AliHajimiriChannel, am curious .. is this an undergraduate or a graduate course in Caltech ? I hope you can answer my question. Thank you very much for this detailed yet practical approach. Most students get lost in the equations but somehow with your insightful explanations, the equations become less intimidating and very helpful in making practical design decisions.
Hello professor,
There's something that I don't understand in the Miller compensation formulas.
When we had a CS stage, as for the output pole of the stage we would say that as we approach the output pole, the input pole is so lower in frequency that it has grounded the input and we can assume it as a ground node.
But in here when we are using the Miller compensation if we assume the same, which the circuit is pretty much the same, we could say that we have an output node with 2 caps, Cc and Cl and one resistor R2. And the input node is grounded. So we can now calculate the output pole (P2) as 1/R2(Cc+Cl). But this is not the same as your answer. Where do I get wrong?
Also thanks for your videos!
I mean what has changed from the C.S. that we cannot use the same logic here?
I would be grateful if you could give me an answer.
@@MahdiMohammadi0 the pole you mentioned did exist for 2nd stage but the moment this pole arrives, it makes the dc gain of the 2nd stage capacitive which in turn reduces the miller effect seen by the first stage. The first stage loading is no longer capacitive, in fact it becomes resistive ( a zero - exactly at the same frequency of the pole " you mentioned"). They both cancel each other and you never see that pole. If you separately plot first stage and 2nd stage gain, you will notice this cancellation. If you plot , overall transfer function, since its already got cancelled , you won't see it.
Prof. Hajimiri, am curious .. is this an undergraduate or a graduate course in Caltech. I hope you can answer my question. Thank you very much for this detailed yet practical approach. Most students get lost in the equations but somehow with your insightful explanations, the equations become less intimidating and very helpful in making design decisions.
This is likely undergraduate, though some universities have dual course offerings so the same course can be taken for graduate credits. Sometimes there are extra requirements for graduate students.
I don't know about US, but in Canada undergraduate and graduate students take the same course. However, graduate students need to do some project requirements from the course, and the project credit accounts for something around 40% of the total credit.
I didnt understand how you calculated the zeros in the system.
In this book : Cmos integrated
circuit design by Razavi
Chapter :frequeny response
Sir why are we performing compensation for the forward amplifier transfer function (until now we were seeing how to get a phase margin in the loop gain, so that my closed loop system is stable). Am I compensating the forward amplifier so that even if I close to loop with a feedback factor of 1, my system should be stable.
This approach assumes that forward amplifier is frequency dependent, but the feedback is not frequency dependent or even if frequency dependent assumes that dominant poles coming from forward amplifier. Hence, in the loop gain system, all the poles and zeros coming from forward amplifier.
This guy knows zip about transistors. No amplifier is purely resistive. There sre internal parasitic capacitors in transistors. He is saying he has a purely resistive amplifier and he wants to add capacitance to make it stable. All unmitigated BS. Anyone forced to listen to his yabba dabba mixed up understanding of transistor amplifiers is doomed to failure as an EE.