Miller Plateau effect within MOSFETs explained - a simple and intuitive approach
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- Опубликовано: 6 авг 2023
- In this video Dr. Ali Shirsavar from Biricha Digital, supported by @OMICRONLabTutorials , explains in simple terms what the Miller Plateau effect is within MOSFETs which occurs during the switch on and off of the MOSFET
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Everyone explains "what" miller effect. But no one answers the most important one, which is the "why", miller effect .
This video is the best one so far.
You are brilliant at explaining things, thank you
Beautiful explanation
Thank you for your great explanation!
Another great video professor!
Greetings from Slovenia
well done Ari, best explanation I ever have seen.
Thanks for the practical demo!
I don't know why youtube recommended this video to me, but it was worth it! (I mean, I do watch videos about electronics once in a while and do design electronic circuits). I knew that the miller plateau existed, but this video made me understand it in the first 3 minutes.
Btw. love the "no we are going to go to the lab" which literally means sitting down right where you are standing 😆.
[edit] there are also a few gems among your other videos! Thanks!
lol, I'm glad I'm not the only one that laughed about this.
Thank you. you are the best teacher.
Excellent explanation. Thank you very much.
Great explanation, thanks!
Great explanation but my biggest complaint about theory based learning has been the lack of real-world context which was not even mentioned, while I understand the complex nature of learning this for the first time, young engineers need to know that you can't just hard switch everything. In the real world EMI will ruin your day! I remember the first time I had to face the facts of EMC qualification and the absolute disbelief that I never heard of it while in college. I'm sure you are aware but just in case someone reads this comment, there aren't many applications that allow hard switching. The trade off between passing EMC and performance is a tough one to swallow. As switching node dV/dt increases the EMI increases. Please forgive me if this topic has a video of it's own but it would be helpful to provide a link to help young players continue the journey to real world proficiency. Not to take anything away from the outstanding job you did here, it's beneficial to learn the real world issues that arise with each subject.
Switched techniques usually save so much energy that the relatively little bit of heat dissipated for conduction during slower switching is often preferable to EMI “fallout”. In economic terms, the higher the product volume, the faster one can switch while still affording the development.
@@absurdengineering "Often preferable" is a little too generous, it's an FCC mandated trade off. Maybe for low power large formfactor applications it's preferable but in todays compact designs it's an EMC requirement, otherwise we're stuck using large transformers/inductors. It's truly a convoluted balancing act where the application determines the best approach.
Thank you
@hardstyle905 Contrarian has entered the chat... Nice of you to join us. I had no idea you wouldn't have your day ruined by failing EMC, you must be special.
@hardstyle905 You commented to disagree and brag about the lack of regulation in china? That's unique position to take, I agree, you are special.
Please more and more videos.
It really helps a lot sir
Crystal clear explanation, thank you
Thank you so much for these videos, love to learn something new!
great work sir, your explaining complicated things so easily
How nice to actually"see" what is happening with the gate capacitance. Would like to see more similar videos.
Wonderful explanation, Thank you Professor
Very well explained. Thank you!
Amazing explanation! Thanks!
Nice video, well done, thanks for sharing it with us :)
Superb, really appreciate it.
Thanks for your great explanation
Thank you!
Thank you for the explanation
Sehr gut! Danke!
Great work 👌
Very nice explanation 😊
Very very very good explain
A nice short, sweet, and perfect explanation with a great teaching method, thank you!
I would like to ask about noise that may be generated due to fast switching, would it be a concern at all?
@jasongreene303 Exceptional observation, the answer to your question is absolutely yes. As the switching node dV/dt increases EMI increases, in the real world you are constantly battling the effects of EMI which is always a performance trade off. As mentioned in the video switching losses increase the slower you turn on the MOSFET. Snubber circuits can help cheat the pitfalls of hard switching a MOSFET but cost and complexity increase. You will always have to keep in mind that even if the circuit works it doesn't mean it's optimized, that's where the rubber hits the road. It would be great if we could hard switch everything but the truth is it's only acceptable on the bench. I suggest reading device manufactures application notes on the subject to better understand methods of avoiding EMC problems. Great question, you deserve a cookie.
@@str8upkickyaindanuts289 You are very kind, thank you.
I have to admit that I am aware of the interference from switching supplies as it makes for some horrible noise in my HF receivers, but I am not familiar with exact circuit design specifications other than the noise I see on a scope in a video such as yours. I wish more manufacturers were responsible about this.
I look forward to perusing your library of information. Thank you
Thank you ...
Thank you ❤
Thanks!
I really appreciate this video
I wish the professor had Vietnamese subtitles
I watched 3 times and seemed got what he meant in details. When Vth just reached at the gate, drain voltage is on the way to be connected to source which is grounded. This is when Cgd will be discharged and then get re-charged at the opposite direction from the positive gate voltage. The plateau forms as the Vgs is “waiting” for Vgd to be recharged before rising up again
I am having issus of IGBTs heating up and tend to fail. I replaced with genuine and same part on the 3KW HB smps. A spike is being generated in the middle of the rise time charging of the IGBT. Tried a lower value than 10R but things got worse. I am afraid if I change to a higher value such as 15 or 20R as this will even slow more the charging time. How can I cure this problem?
Suggestion add mark-up to video showing where the drain voltage dv/dt is. Just to confirm
Nice presentation. They should invent a screen grid for mosfet
Some of the early mosfets from the early 1970s were 4-terminal devices, having two gates. This made them good rf amplifiers as you effectively had a cascode arrangement which minimised the Miller effect by fixing the voltage on the upper gate, thus clamping the voltage on the drain of the lower part.
@@RexxSchneider yes I realised cascode a short while after I wrote the comment but rather than delete it I thought make a fun comment for someone to read. Cascode goes back to thermionic valves probably further.
I've had great fun with 3N201s and 3SK88s and the like. The great thing about them is a pair makes a superb balanced modulato. These dual gate mosfets also make a fabulous VFO oscillator output buffer with nearly infinite isolation. Also make great AGC control elements in a IF amp.
can you explain why the capacitance moved at 2:34? not sure why turning on the MOSFET changed the capacitance. thank you!
Is there a point where the device can be biased to exhibit neither the plateau nor the overshoot (as displayed on the oscilloscope)?
In the turn OFF, there is only lets say 5V difference between the Gate and the source, instead of the 100V difference. Can someone explain that please?
Meaning slightly fast switching... let's say 15 ohms gate resistor will be enough to minimize ringing and getting slightly fast switching?
How does the Miller Plateau effect MOSFETs in audio circuits? And is it a concern?
But my doubt is before reaching to miller platue why current doesn't not flow through the CGd ? Lets say your drain node is fixed but when it's charging Cgs then bottom node voltage is changing then there should be current flowing through the Cgd also before Vds starts falling out..
The Miller effect occurs because there is voltage amplification between gate and drain. As the turn-on threshold is reached and the mosfet begins to turn on, a small increase in gate voltage produces a much larger decrease in drain voltage, and that applies a negative feedback via Cgd. So the gate voltage cannot rise, nor the drain voltage fall unless current flows to discharge Cgd. That is the Miller plateau.
huh! like phase change enthalpy?
It's a kind of bootstrap capacitor.
سلام اقای شیر سروار اگر کانال یا پیج به زبان فارسی دارین ممنون میشم معرفی کنید .
if the aim is to reduce the miller plateau then why do we put the gate resistor in the first place .. ?
The gate resistance here is not always physically placed component but simple representation of gate drivers output current limitation.
@@kadamrohan16 I have seen an external gate resistor used often in gate driver circuits. It may have some other purpose.
Many times they use it to damp gate ringings.
The MP is always there and it's a secondary effect. It's like lights go dim when switch a big motor on.
By watching 'lights go dim' you can detect when there's a current drain.
A capacitance is equivalent to an instantaneous short circuit and there must be some limit to the current drawn from the driver. Either the driver limits that itself, or we put a gate resistor in series to set the maximum current drawn. An additional consideration is that if the driver switches rapidly -- and we normally want it to -- then any inductance in the line from the driver to the mosfet gate will create a closed LC circuit via the grounds of the diver and mosfet source, which will cause ringing, or even oscillation, unless it is damped by sufficient resistance in series.
hello
There is an additional charge from gate to channel you have ignored in this simplified analysis . Once charge starts to flow in the channel and equal amount of charge must be supplied to the gate. This is fundamental to all three terminal devices to which are governed by charge control model in their linear operation regions. Why did you ignore that charge?
He just explained the miller plateau caused by the nonlinear capacitor Cgd
Hi Dr. Shirsavar, what is causing differences in CH2 curve - Vds, if I used this 2 FETs ? Qg or Coss ? Is there also impact from different Qrr and trr ? ruclips.net/video/HMUD1pbp6eA/видео.html
those drawing could have been better imo
Explanation is not great…