Yes, but doesn't fully shield the H-Field component unless it's a special mu-metal designed to do that. Nickel screening alone mostly works on the E-field component, but only has about 1/100th the permeability of MuMetal so it's not that great on the H-field.
What’s really hard is trying to shield low frequency signals, it was once described to me that trying to stop 50/60 Hz is equivalent to trying to stop a bullet with tinfoil. High frequency of hundreds of MHz or GHz that a modern laptop would produce can be pretty much stopped by nearly anything in its path.
npgatech it’s not just black magic to some of us, it’s black magic to ALL of us lol... there’s principles you should follow, but a way to engineer this problem out of existence would be impossible, it’s so dependent on each design. I’ve had job interviews where the chief engineer would desperately ask if I had any EMI compliance experience, because they had failed the test so many times and didn’t have a clue what to do about it... if you end up with a product that’s badly misbehaving it can be a real nightmare even for professionals that specialize in this type of work... the problem you will face is not learning the techniques, it’s the massive expense of it; it’s stupidity expensive to test EMI, and without testing you will have no idea where you are. You need really expensive gear just to start asking if your efforts did anything at all...
This is so nice to see the effects directly and the difference between 2 and 4 layers. I made a lot of PCBs for my DIY projects that are using radio connection. I always had problems with the radio module because the SPI for that was very "sensitive", but once I place that on the exterior of the PCB and made a ground and Vcc plane, the board had no more radio errors. Especially that my board was using PWM signals and MOSFET control and that made a lot more noise. Thank you for all that you show us!
I'm an electrical engineer and I love these type of videos. I'm still pretty young a very hungry and eager to improve my skills. Work for a large company and so there are other engineers whose careers have been dedicated to Signal integrity. So I don't really get to learn this as they are the ones who are the real experts on these topics. Then again I don't think we've ever done anything smaller than a 6 layer board. We ground flood the top and bottom layers and all signals are inside the board. That's how they deal with Emi and EMC. They just surround everything in ground. Please do more videos on practical engineering tips and tricks. I enjoy these types of teaching the young engineers much more than I like an unboxing video. I do really like your tear-downs to as they can teach a lot
Great job Dave. I love your video not only the technical aspect, but the way you spit out your knowledge with so much emphasis. Keep doing more and more video.
This is great, the first time I have ever seen someone do this on the same pcb as a 2 layer and 4 layer with groundplane. Thanks Dave this is a really really useful emc video.
Thanks. Can't say I've seen it anywhere else either which is why I was interested in doing it. Perhaps another video with a 6 layer version with ground planes on the outside layers?
EEVblog You video should be used in electronic schools! Why not make the top and bottom layers ground with the traces and power layer internal? Would that make it super shielded?
@@Daveyk021 lol. Maybe it would. On the other hand, having had to do amateur fixes to old electronics at times, the thought of having all the critical traces being internal within the board kinda gives me nightmares... Multilayer boards in general can be a bit intimidating when you're trying to figure out what the circuit looks like from the PCB traces alone. When large chunks of the traces are effectively invisible... Well... Yeah. Good luck. >__
Make more stuff like this! There is so much stuff we are told about PCB layout best practices that we take for granted but an engineer doesn't have time to make all these mistakes for themselves.
If the shorter path has lots of vias the current distribution might not be that obvious, as it favors the path of least impedance, whereas vias can have high impedance for higher frequencies
An interesting measurement would be to take a bare (unstuffed) board and measure the capacitance between Vcc and Gnd to find out how much filtering it would be.
Back in the 80s I had a TRS-80 model I, which did not have true audio output. There was a program that got around this limitation by intentionally generating EMI that could be picked up by a radio placed near the computer.
Loop area is critical. But there can also be resonances, which can actually amplify harmonic noise. So, solid ground and power planes and a good assortment of decoupling caps is the way to go. FYI, I recommend you take a look at K-SIM at Kemet.com. It's a handy free tool for choosing your bypass caps. Shows a nice Bode plot.
What’s a real pain these days is getting power consumption low while not having ridiculously fast rise times on the board, thankfully most hyper fast signals can be held within the small confines of the ICs themselves or we’d be in real trouble. Impedance matched low voltage tracks with pre emphasis becomes hard to avoid.
Need to split ground planes for e.g. analogue and digital processing on the one board. Not to mention high voltage stuff! Ground loop is your friend if you treat it well.
Test house charge excessive amount of money and time to test a board. I'd rather use cheap tools like these to asses my board's EM characteristics.. Thanks for the video Dave and hope you will make more on videos on tackling EM at design phase.. maybe start a new project and show decision making process at each stage of PCB designing..
With 4 layer boards, there's often a much bigger gap between layers 2/3 than between 1/2 and 3/4. But power planes work best when they are tightly coupled with each other. So, assuming you did L2 ground and L3 power, you would have benefited from keeping the copper pours and tying the pour on L1 to power and the pour on L4 to ground. This would increase the interplane capacitance between power and ground significantly, and with proper stitching it would also make it much easier for signals on L4 that reference the power plane to transition to L1 - because the return current can ride along a power pour, instead of searching for a bypass cap so it can switch to referencing ground. For the truly paranoid, you can put the planes on the outer layers, and it will act like a pseudo strip-line. But in that case you REALLY need to have pours of alternating polarity to the reference plane, because the interplane capacitance will be greatly diminished if your planes are L1 and L4. Rick Hartley has a lot of very nice videos if you want to explore this topic in more detail.
Coming back two years later to see if there was ever a follow up, cause it was super relevant at the time! Nope. Nothing. Anyways, my mantra in college became "If you can understand it drunk, you can understand it sober." But to this day, I can only understand Laplace transforms after at least 5 beers
EMC compliance testing isn't always in the far field. Most of the time it is but some standards test lower frequency H-felds (loop antenna) or E-field (typically 41" dipole antenna) in the near field. Military and some aviation is famous for this (E-field) however some rail standards as an example test H-field. Dav is correct about nearfield probes not directly correlating to lab compliance but targeting big peaks or broadband is always worth while prior to hitting the compliance lab. Just don't forget the cables, sure the emissions are conducted onto a cable however this cable will radiate, potentially greatly.
14:18 yet another occurrence in the wild of 2pi... it’s too bad that particular paper of Euler’s was used to popularize pi, where he compared semi-circumference to radius (~3.14), instead of one of the ones where he used the full circumference on radius (~6.28). Ah well. At least we’ve now got a name for C/r as well. Hopefully it’ll continue to catch on to a sufficient degree that in another 80 years, few people will remember what pi is... but they’ll know about tau. :) (And for anyone who’s just hearing about this for the first time, see tauday.com.)
I wish you would have briefly shown the added GND and VCC planes in the CAD software. It's basically just left up to our imagination about how it looks. I have a feeling it's a solid copper rectangle, but with with holes everywhere punched through for isolation from the component legs and vias. For the connections, some kind of thinner traces, usually 4 in a + shape, attaching from the plane to the relevant plated thru holes so the pins can be soldered easier as then the heat isn't wicked away. But without seeing it, as I said, it's left up to our imagination.
Hi Dave, Nice education video and thumbs up. For me, this video has been an eye opener, how layers with power plan make difference in EMC ! Could you pls also let us know, how about having a single layer PCB? - will it generate lower or higher EMC? Any actual comparison please. I usually work with two layers mostly and single layer in some cases. It gave me a learning to follow the datasheet for the EMC sensitive components, where they recommend to have a separate plan and also no power trace underneath the chips etc. Now I understand it better. Thank you once again for this video.
The 4 layer board shown has the power/ground planes in the middle. What would be the radiated difference if it were reversed, with signals inside, and power/ground outside? I admit that debugging the layout would be terrible, but once it is working, would it make a difference to reverse things?
First thing I thought when seeing the layout of the 4 layer board ;-) Will be quite interesting to see the difference it makes! Let's take a wild guess: another 10-15dB?
Expect it will give some improvement as the signal traces will be in a faraday cage. In practice this would be of limited relevance since with SMT the component pads are on the outer layers, and you don’t want to add vias for every signal pin....
What would happen if you instead of Horizontal traces Ground 5V Vertical traces you had Ground Horizontal traces Vertical traces Ground Would having the ground planes on the outside act as a shield?
I had the same question, it offcorse hide all traces within the board (nightmare to patch or repair), and the 5V will have to bounce a lot between two floatfills areas on layers 2 and 3 I suppose
That is common practice for that exact reason. But in this case ditching the power plane for an extra ground plane is a bad idea. From an AC perspective, 5V and GND are the same (thanks to all the decoupling capacitors) so 5V Horizontal traces Vertical traces GND would be almost as good EMI-wise and make for a much better power distribution network.
There's a book that's generally considered 'the bible' of EMI. It's by a man named Henry w. Ott. In this book he says that this is the best stackup you can have besides using a 12 layer board! Even better than 6 and 8 layer boards!
@@lyfeofajavadevwithfrank9813 Thanks, I found his website. "the two ground planes can be stitched together around the periphery of the board to enclose all the signal traces in a faraday cage. ". NOICE! www.hottconsultants.com/techtips/pcb-stack-up-2.html Two of these three problems can be alleviated with the stack-up shown in Fig. 3b, where the two outer planes are ground planes and power is routed as a trace on the signal planes. The power should be routed as a grid, using wide traces, on the signal layers. Two added advantages of this configuration are that; (1) the two ground planes produce a much lower ground impedance and hence less common-mode cable radiation, and (2) the two ground planes can be stitched together around the periphery of the board to enclose all the signal traces in a faraday cage. From an EMC point of view this configuration, if properly done, is the best stack-up possible with a four-layer PCB. Now we have satisfied objectives, (1), (2), (4), and (5) while using only a four-layer board. _____________ Ground. _____________ Sig./Pwr. Figure 3b _____________ Sig./Pwr. _____________ Ground
im amazed **my** TTL machine works at all then. my ground planes are split to hell by signal traces with minimal to no stitching, only enough to appease the "unconnected net" rule.
Interesting stuff never really considered that traces basically generate loops, makes sense. I imagine things could get interesting if the signal frequency happens to match the resonant frequency of the loop then it's basically a transmitter. I imagine this is something that has to be accounted for on very sensitive and high frequency systems like computer motherboards.
@@deelowe3 I'm of course talking about RF, using the term EMI for light and higher frequencies would be a bit silly, even though both are electromagnetic radiation.
@@RobertSzasz most of it is actually EMI, and most of that EMI is caused by switch mode power supplies. The efficiency and price is great, but it comes at the cost of a fuckton of EMI when not done perfectly (and it very rarely is done properly)
mmh. I've got an Atari 800XL under my desk, and the shielding on that thing is pretty crazy. And the thing is, that's the shielding AFTER the FCC relaxed the rules quite substantially. The original design of these computers were notoriously built like tanks, from really heavy metal casings. And all of that was to meet FCC compliance. So... Double layer computer boards huh. XD Funnily enough though, the Commodore 64 towards the end of it's life was using cardboard with a metal coating for shielding. The atari never got to that stage, and remained solid metal shielding, but... It's kind of amusing to think what companies did back then to somehow meet the compliance standards AND cut costs to the bone...
Great video Dave, I'm really into PCB cadding at the moment using Eagle 7.5 (Professional) thanks but has anyone noticed you spelt Wavelength wrong? (12:53) DOH! ;)
Great video, thanks for this video. Could you make a video about difference in Conduction Emission between 2 layer and 4 layer boards as you use in this video. Use the current probe for the graphics and other connector and LISN 5uH for the power supply and check the Conducted emission up to 200 MHz. Thanks
@EEVblog what I wonder is . If one would sandwich the the 2 layer traces(original pcb) and make the outside layers a ground-plane (on the 4layers).. would that dampen more? Is there a reason why you went for a ground-plane in the internal layers and not the outside layers? This is actually a thing that I would think makes a difference ( looking at it without knowing the maths ). I love to know where science interferes with my common (miss)conception.
I would have to assume if you redid this with a full ground plane on each of the outside layers, it.would reduce more? May make it a pita for other reasons but.
Here is an interesting question - would ground filling on a 4 layer board help with EMC? If the clearance from trace to ground fill is smaller than the distance between the outer and inner layers, shouldn't it make a difference?
Just a thought; I don't think you - generally - would be able to get significantly lower inductance and higher capacitance from a flood fill than from an adjacent ground plane. Even though you might get slightly closer to the ground fill with tight tolerances on clearance.
@@mr_gerber - The PCB trace acts like an antenna, and , all antennas emit electromagnetic waves at the standing wavelength. The switching digital current generates a wide spectrum of higher frequencies harmonics, the question was by carefully adjusting trace lengths , perhaps some of those EM emissions could be suppressed or entirely eliminated.
Would the program being run and its constantly changing state affect the radiated emissions? Enough to make it pass compliance by having a rom that uses reduced processing power?
Hey everyone, I need your help. I am currently building SMPS on tl494 chip. But I am little bit confused about kick starting the chip. Can i use 200k resistance between mains 300 volt regulated DC supply and tl494 chip to kick start it with some 22uF cap?? is it safe way to power it up?? I'll power it later on with auxiliary winding with rectification for running the chip continuously. Operating voltage of TL494 is 7 to 40 volt.
Hi Dave, great stuff as always. can advise on an EMI source for testing the performance of a circuit under the electromagnetic field of about 3 V/m in a lab in a range of 80-250mhz?
Makes more sense why a motherboard has like 8 or whatever it has. Plus our FCC regulates along with IEEE, ANSCII, etc. So US Yankees, Lol, get to turn that silly spread spectrum OFF!! Not normally an issue, but for avid overclockers everything makes a difference.
Hey Dave, was this video uploaded (not released) before 29.01.2019 UTC time? I could swear RUclips is using unpublished videos as a source for recommendations, I watched Bil Herd's (from Hackaday) video on PCB Impedance where he explains the relationship between current loop area and magnetic field strength, recommended by RUclips just about 2 days ago...
I am a PCB designer in a small electronics designing company and we are aiming a lot on the low price, so most of thw stuff we do is 2 layer. It caused a lot of problems to us when we go to EMC testing. Biggest problem is the fast switching, you can put 10R to 22R resistor in series in the high speed traces, this helps a lot. Also keep your traces as short as possible and always look for the ground loop.
Yes, it is an excellent idea to put small resistors in series with the IC outputs that drive high speed traces. This helps control the edge rates, reducing radiated emissions. It also reduces the current spikes as the high speed outputs drive the capacitive loading of the traces, vias, and other IC input pins.
The resistors typically allow you to match the impedance of the trace. This stops current sloshing around hence lowering emissions. Think of a wave in a bath of water. Now put some form of blockage in the path and you will see ripples all over. This is what impedance mismatches are. You are trying to make everything look the same to the wave fronts. A better analogy is your tyre across a dirt road and the suspension. Fill in the holes and you creat a smooth surface, or remove dirt piles and create a smooth surface.
@@ZeusandHades You use a Signal Integrity simulator tool. This calculates the impedance of the trace based on the characteristic impedances of the materials of the PCB. Ie using microwave stripline and microstrip modelling. You could do it by hand too (as we did in the old days) using microstrip and stripline formulas (there are books and internet resources - ARRL HAM manual has a lot of info in). Tools such as Altium can do this for you too but for better quality Mentor/Siemens Hyperlynx and Cadence’s Allegro SI package. There’s also Ansoft RF tools too and a few others.
To be more accurate you use IBIS models Io Bus Interface Standard which also models the Inputs and outputs of various ICs on your board. This allows you to simulate the whole signal chain and the trace and figure out the correct termination scheme. I will add that this can be fairly complext to get right if you are working on SerDes or other very fast signalling technologies. It’s a field in it’s own right.
Do you have any opinion regarding the pros and cons of having 4-layer boards with the power-planes as the outer layers and the signal tracks on the inner layers, versus having the signal tracks on the outer layers and the power-planes on the inner layers?
@@MaxWattage 1. Propagation delay is higher for internal layers. 2. You'll need a ton of vias, that would break up the ground/power planes and that wouldn't be great for return paths. Also reducing vias on high speed signals is desirable. 3. It would be difficult to rework the board if needed.
@@EveryThingTechet Points 1 and 3 you are correct. Point 2 is completely wrong. It wouldn't make any difference to the number of vias. You could simply swap the layers but still use the same artwork. You could actually REDUCE the numbers of vias by using blind/buried vias which you can't do with the signal layers on the top and bottom.
@@mrgibbo63me46 nah it really would increase via count. Depending on the board, you could add a ton of vias. Some signal traces wouldn't normally go into the middle or bottom layers, but to make a ground plane on the outside you'd have to add 2 vias per trace.
@@TheRealMonnie Definitely true for an SMD design. Through hole like in this video - the layer orders would not affect via count. You want the power/GND layers to be close together though - increases capacitance between them. There is something to be said for having further GND on additional outer layers and the Faraday shield effect. High speed data is often sandwiched between 2 GND layers to maintain transmission line impedance.
Awesome video! Seeing a side-by-side with identical boards with different layers is something that many of us have never seen done. Quick question: What would the difference be if you reversed the layers and did the traces internally and the ground and 5V externally? Thanks so much for your efforts, Dave!
@@EEVblog I would love to see that. Also, what effect does placing a ground "ring" around the outer perimeter of the board that attaches to the device connector shields and then attaches to the board ground plane through capacitors? I know that technique is for ESD protection, but does it help to reduce EMI at all? If you want to see an example of what I'm referring to, you can look at the BeagleBone PCB files. They have that "ground" perimeter on every single layer of the board, not just the outer layers that connect to connector shields. Does that have to do with the high-speed DDR or HDMI signals that are on the board?
With a board with 100% through hole components, not much difference except for the better shielding of the signals that now are inside a shielded box (planes on the outer layers). In a board with SMT components it makes a big difference, since having ground/power internal layers means they are almost a complete plane with no voids, while if they are on the outer layers, you have all the pads of the SMT components creating voids and discontinuities in the planes which reduce the effectiveness of the planes. But if you are really concerned with emissions and you have money to spare for a couple of extra layers, you can fill top/bottom layers with ground (only if there is another solid ground internal plane) plus ground ring on the edge of every other layer and use lots of vias on the edges of the PCB to make the PCB like a shielded box for all the signals in the internal layers. Mentor Graphics wrote a book about how using top/bottom layers as ground helps to reduce the number of layers (on board with 16+ layers) since it means bypass caps don't need a via to ground (otherwise every bypass cap has a via to power and one to ground). Also the pair power/ground planes creates a capacitor which is part of the power distribution network to the high speed chips. Changing the position of the power/ground planes in the PCB stackup will change the capacitance and the inductance. FPGA (or other highs speed ICs) companies have lots on apps notes on this topic.
FCC Part 15 is the compliance regs in the US. In the late 70's these new personal computers (Apple II, CP/M systems, but NO IBM PC, yet) plus video game consoles, and other microprocessor based products needed to be added to the compliance standard. So subpart J was added. The whole Part 15 reg has been since realigned, so there is no subpart J anymore. I'm old enough, and had was in the electronics business when subpart J was added. The company gave me the task of making sure our product designs complied with the new regs. Some of these RFI/EMI testing houses are better than others. The first one we went to just ran the test, and we had to fix it back at the shop, before retesting. Another house, let us try things while at their facility, and ran shortened tests to check our intermediate results. They also gave us suggestions. That was a good test facility ! Now products come out of China, and testing boils down to applying a compliance sticker.
Of course testing is still required, but is it actually performed. The thing is when Chinese products are sold directly to customers on websites like eBay, then the testing might be just a sticker. The importing party is responsible for compliance, and when this importing party is a end-user who doesn't know or care about compliance, then the Chinese manufacturer wouldn't bother performing tests. When I have a company importing Chinese electronics and reselling them, then I must be sure they're complaint.
GromBeestje That’s a downside of importing items. If it has a compliance label then it also has an associated number that you can check. Some stuff I have seen has no compliance at all, or only domestic compliance (which may be tighter in some cases - particularly when you have Trump toadies in charge of compliance). Retailers are always liable for what they sell, and certainly here items are anonymously bought by compliance authorities and sent to labs for verification. If they don’t comply then the retailer must recall the item(s). I’ve seen it happen with appliances a couple of times, and often with infant and children’s clothing and the like. Regulation is a necessary part of a functional society.
heh. I have a lot of old game consoles and computers around, and it's interesting seeing the progression in the shielding. Also the history of some designs. Like the 800XL vs it's predecessor from 4 years earlier. Mostly the same internal components, but the shielding... The early 80's variant has some pretty hefty metal shielding inside the plastic outer case... But the late 70's variant is basically all metal construction with an additional, very thick inner layer of metal just for shielding purposes. Because at the time it HAD to be to have any hope of meeting compliance standards, yet a few years later near enough the same internal hardware could get away with comparatively flimsy and insubstantial shielding. (still extremely heavy shielding compared to more modern devices though.)
KuraIthys It’s more a case of not knowing how to meet the standards, so ensuring compliance by excessive shielding. By the early 1980s it was easier to include EMC compliance testing in the R&D process.
If you decide you want to make a heat map of the emissions, using the Python imaging library (PIL/Pillow) combined with an XY table (to line scan the board) and a way to get the data into a computer would be really neat!
Great stuff! I've tried to find information on the internet, but there's so much conflicting information on doing good PCB layout. Videos like this really help. More, please! How about splitting up four layer board ground for isolating sensitive areas? Can't find any reliable info on how to do it. Some recommend star ground, but I never manage to figure out where to put the center node for best effect. Anyway, thanks again.
Frans de Bruijn Looking in random data sheets for this is going to be hit or miss, as different writers and skill levels will be used from one datasheet to the next.
@@johnfrancisdoe1563 The datasheets often show the component layout with ground isolation for components that have both digital and analog components. T.I. has the board layouts for their evaluation boards available for download, thats a good start to see how they do things. There is also some software called AppCad that you can use for calculating the impedance of tracks if you want to design controlled impedance boards. this is especially important when you are working above 20mhz clock speeds.
The information is conflicting because people try to compress a complicated subject into simple rules of thumb and this rarely works in EMC. As for splitting ground planes, I'd try to avoid it. It can have benefits, but the risks are much bigger and it's full of traps. 9 of 10 times a single uninterrupted ground plane will be best. As for information online, check out Henry Ott's website and the book EMC for product designers.
Great video. A couple of questions: 1) On a 4-layer PCB, is there any significant difference between a SIGNAL-PLANE-PLANE-SIGNAL and a PLANE-SIGNAL-SIGNAL-PLANE arrangement? 2) Are GND+GND and GND+VCC planes equivalent? My guess is that: 1) PLANE-SIGNAL-SIGNAL-PLANE would be slightly better for radiated EMI because it traps the noise inside the PCB, but that also means it will slightly degrade the signals. 2) Shielding would be equivalent but GND+VCC planes would be better than GND+GND as it lowers the impedance on VCC nets, also the GND+VCC planes would form a wide bypass cap which might help at very high frequencies. Any thoughts? edit: Just realized several people came up with the same questions :)
I've done one for conducted mode emissions. I might do another one on mains conducted mode as I have some kit for that. But radiated requires a decent antenna and either an OATS or chamber, or at least something half decent.
@@EEVblog I just passed EMC compliance testing for FCC in north america last weekend. I had some issues with the 200MHz region on my board just over the limit so I tried some bench top probing like in the video with no luck. No matter what I changed, little difference was seen. The issue was the external connections to the PCB were acting as antennas, transmitting trash. A few properly sized ferrites and I was able to obtain one class lower then was the original target.
I was thinking about that before he mentioned it, definitely would be neat to setup a rig for that. Kinda like a CNC machine and you put the board in and it just slowly tests each spot. The same rig could perhaps also be used for taking very high res photos of PCBs. Imagine doing something kind of like google maps but with PCBs.
Yes, I was thinking a printable detector for a 3d printer, Dave did say he was going to show how to "roll your own detector" now we could print a clip on case that attaches to a 3d printer head like my creality ender 3 and boom a few hours work and you have a very high spec 3d EMI scanner! the ability to create 3d plots would be of immense use for problematic layouts and great ones too, the ability to log the EMI values in 3d space will lead to all sorts of clever solutions... just a brilliant idea.
It also raises some interesting points too, like getting the DUT to behave in stable consistent way over time, as the scan progresses you don't want the test device changing power levels or turning on and off antennas etc.
You missed the *3rd* orientation by having the probe vertical (looking at the video). It might help to determine if a problem is with horizontal left right traces versus vertical up down traces.
Haaaaa the joys of EMI compliance. Love the Tekbox probes I have the same kit with a Siglent SA3021X spectrum analyser, awesome for the price. I also built clamp on RF probes with ferites (Wurth electronics makes great ones) works great to measure radiated emissions from cables and see the difference cable impedance can do. Today there's no reason to not do EMI pre compliance testing in house, it saves a bunch of money and time.
Interesting. FWIW, a coil like that measures the magnetic flux though the coil, so when the coil is flat you're measuring the vertical component of the H field.
Great credit to Dave for going to the effort of making this board and exhibiting the measurements! Some of Dave's videos can be relatively blab or rant oriented, of which there is much on RUclips :-), but videos like the current one really distinguish this channel. Well done Dave!
EEVblog: EMC, EMI, traces, power rails ME: b23.tv/zZwnaX 5V 6A, 124 chips from DIP14 to DIP40, no bypass cap at all because there is no room for them at all even for MLCC, thousands of randomly placed signal traces in 3mil or 8mil which of course obviously cannot be routed by hand, you can even hear chips whispering with just a capacitor and an earphone and you can even debug the program with these noises and tell what program it's executing because each piece of program has it's own unique noise, and the most surprising thing is it can work, just with some tiny little small glitches, probably
Would it make a difference if the signal layers were sandwiched in between the supply and ground planes? Wouldn’t they act as outer shielding? Just guessing, sorry for my ignorance
This is black magic only because it's very hard to quantify specific causes and effects due to the different nature/characteristics of each circuit. The possible sources for the EMC issue are very well known, however. This video addresses PCB layer aspects of EMC, but the total solution is much more difficult to cover in one video. Check the list below and religiously follow as much as you can. Research each item one by one as time permits. Each item is worth a chapter or two in a textbook. Surprisingly, if you follow these guidelines, then you'll enjoy saying "what EMC problem?" for the rest of your career. It starts at the design stage. 1. One de-cap per power pin, yes per pin not per chip, placed close to the pin(
Dave! That clip of an anechoic chamber looks exactly like an acoustic anechoic chamber with the sound absorbing wedges. Why would that be needed for radio frequency measurements, or are they different material???
Yes, a completely enclosed pcb cannot radiate beyond the enclosure. The problem is that there will always be some openings in an enclosure that allows the emissions to leak out. Or the same emissions couple to wires leaving the board through the enclosure.
Regarding the heatmat, a rather different ("real") kind of heatmap I have seen many years ago in a video (that I can't find): The guy took some thin layer pcb ground planes (full, with split etc.), painted them black and took some prepreg with signal traces, overlayed them and then ran high power high frequency signals through them. In the end he took an image with a thermal camera. The result was very neatly showing how the low frequency components chose the intuitive shortest path, but the high frequency ones were following the signals, or spreading out in places nobody would have thought of.
i remember being able to hear my Amstrad CPC464 on FM band when loading games!..i guess it was due to be cpc being built as cheap as possable without any sheilding what-so-ever!
I love your explanation about near and far field extra to the main subject. When it comes to layers, I newly redesigned an RF board (up to 6 GHz) from 4 to 6 layers. A lot of other changes had to be made, mostly because of the last problems with delivery of the components and because of the heat issue. But I have taken care of the appropriate routing of the RF lines and of grounding in general, in the same time REMOVING many decoupling capacitors (after watching Eric Bogatin presentation at Altium Live) and... the PLL on the board is soooo less noisy!! The biggest Spourious reduced from ca. 30 dBc to less than 50. Sadly I could not compare the grounding alone so nicely as you did
it is not simple to think, 4 layes is like a huge capacitor which smooths the rising edge, and that way it lowes the EMC?. I means, two solid middle layer plates, which in parallel with all tracks?.
Ground planes are a must for high frequency digital designs, but I was not expecting such a big difference for these low frequency boards. Pretty instructive, thanks for the video!
Hi Dave, many thanks for the valuable contents. I was wondering if you have / intend to do a tutorial on how to route mixed signal boards, how to separate analog and digital Vccs, GNDs planes. Thank you
I LOVE when you do EMC Videos.... My companies units need to be compliant to EN12895 for our systems. I found using a Walkie Talkie is an excellent way to perform some precompliance Radiated Immunity Testing. You should try it out Dave.
If emc is the reason for using a 4 layer board, why not put the signals on the middle two layers? Put the solid power layers on the outside. Yes, you lose some of that free decoupling you would have gotten from sandwiching the power planes closer, but the two layers survived without it, so it's not necessary.
This was super helpful! Thank you. Short loops, via stitching and watch out for bypass caps. Perfect timing for a current project as well. Still killin' it after all these years!
Yes please on more EMC / EMI videos, especially radiated. Basically what you can and can't get away with in a design and pass compliance testing. And what you can and can't derive from a semi-affordable pre-compliance testing setup. Examples of topics I'd love - I'd especially love to see comparisons between lab measurements, DIY antennas and middle road spectrum analyzers like your Siglent and Rigol, DIY OATS , the probes as you did in this video, semi-anechoic chambers, and *especially* with TEM cells since they're supposedly usable in lieu of a proper OATS. How to properly setup and run the equipment to test against compliance standards for intentional and unintentional radiators.
Good work Dave, amazing video. I have never seen a 2 to 4 layer PCB comparison before, and to have a board for the test with this level of complexity is really a bonus.
So this is what the metalised plastic on cheap laptops is for, shielding the board from radiating EMI. Neat.
Yes, but doesn't fully shield the H-Field component unless it's a special mu-metal designed to do that. Nickel screening alone mostly works on the E-field component, but only has about 1/100th the permeability of MuMetal so it's not that great on the H-field.
@@EEVblog could you please do an smd vs th emc?
kapios kapiopoylos There would be hardly any difference if you kept the layout otherwise identical
What’s really hard is trying to shield low frequency signals, it was once described to me that trying to stop 50/60 Hz is equivalent to trying to stop a bullet with tinfoil. High frequency of hundreds of MHz or GHz that a modern laptop would produce can be pretty much stopped by nearly anything in its path.
npgatech it’s not just black magic to some of us, it’s black magic to ALL of us lol... there’s principles you should follow, but a way to engineer this problem out of existence would be impossible, it’s so dependent on each design. I’ve had job interviews where the chief engineer would desperately ask if I had any EMI compliance experience, because they had failed the test so many times and didn’t have a clue what to do about it... if you end up with a product that’s badly misbehaving it can be a real nightmare even for professionals that specialize in this type of work... the problem you will face is not learning the techniques, it’s the massive expense of it; it’s stupidity expensive to test EMI, and without testing you will have no idea where you are. You need really expensive gear just to start asking if your efforts did anything at all...
This is so nice to see the effects directly and the difference between 2 and 4 layers. I made a lot of PCBs for my DIY projects that are using radio connection. I always had problems with the radio module because the SPI for that was very "sensitive", but once I place that on the exterior of the PCB and made a ground and Vcc plane, the board had no more radio errors. Especially that my board was using PWM signals and MOSFET control and that made a lot more noise. Thank you for all that you show us!
Yep, can make a huge difference when you have an intentional high-ish power transmitter on your board!
I'm delighted to see this high-quality educational content.
More EMC videos are welcome :)
I'm an electrical engineer and I love these type of videos. I'm still pretty young a very hungry and eager to improve my skills. Work for a large company and so there are other engineers whose careers have been dedicated to Signal integrity. So I don't really get to learn this as they are the ones who are the real experts on these topics. Then again I don't think we've ever done anything smaller than a 6 layer board. We ground flood the top and bottom layers and all signals are inside the board. That's how they deal with Emi and EMC. They just surround everything in ground. Please do more videos on practical engineering tips and tricks. I enjoy these types of teaching the young engineers much more than I like an unboxing video. I do really like your tear-downs to as they can teach a lot
Great job Dave. I love your video not only the technical aspect, but the way you spit out your knowledge with so much emphasis. Keep doing more and more video.
That's the plan
Thank you again Dave for sharing your knowledge and wisdom, I am finally able to wrap my head around this.
It used to be a challenge to route everything on a 2 layer board. Since I've had a couple of products compliance tested I go straight to the 4 layers.
Yeah, not much cost difference these days.
I have never designed a PCB but I am an engineering student and will soon start. This was very informative, as always with your videos.
This is great, the first time I have ever seen someone do this on the same pcb as a 2 layer and 4 layer with groundplane.
Thanks Dave this is a really really useful emc video.
Thanks. Can't say I've seen it anywhere else either which is why I was interested in doing it. Perhaps another video with a 6 layer version with ground planes on the outside layers?
Or even a four layers with the ground planes on the outside.
Yeah, doh, layer with ground and power outside. Crosstalk signal integrity on signal layers isn't really an issue here.
EEVblog You video should be used in electronic schools! Why not make the top and bottom layers ground with the traces and power layer internal? Would that make it super shielded?
@@Daveyk021 lol. Maybe it would.
On the other hand, having had to do amateur fixes to old electronics at times, the thought of having all the critical traces being internal within the board kinda gives me nightmares...
Multilayer boards in general can be a bit intimidating when you're trying to figure out what the circuit looks like from the PCB traces alone. When large chunks of the traces are effectively invisible...
Well... Yeah. Good luck. >__
Identical PCB, except for the audio out socket?
I expected to be a difference of -3db to -6db.
This difference you've shown is incredible!
Make more stuff like this! There is so much stuff we are told about PCB layout best practices that we take for granted but an engineer doesn't have time to make all these mistakes for themselves.
If the shorter path has lots of vias the current distribution might not be that obvious, as it favors the path of least impedance, whereas vias can have high impedance for higher frequencies
An interesting measurement would be to take a bare (unstuffed) board and measure the capacitance between Vcc and Gnd to find out how much filtering it would be.
Back in the 80s I had a TRS-80 model I, which did not have true audio output. There was a program that got around this limitation by intentionally generating EMI that could be picked up by a radio placed near the computer.
Probe + some servos -> planar near-field scan -> near-field back-projection. The "near-field back-projection" would be interesting.
Loop area is critical. But there can also be resonances, which can actually amplify harmonic noise. So, solid ground and power planes and a good assortment of decoupling caps is the way to go. FYI, I recommend you take a look at K-SIM at Kemet.com. It's a handy free tool for choosing your bypass caps. Shows a nice Bode plot.
Absolutely, I mentioned that in my bypass capacitor videos.
What’s a real pain these days is getting power consumption low while not having ridiculously fast rise times on the board, thankfully most hyper fast signals can be held within the small confines of the ICs themselves or we’d be in real trouble. Impedance matched low voltage tracks with pre emphasis becomes hard to avoid.
Great tool! Thanks!
Learned very much from this video. Thanks Dave!
This needs to go viral
Need to split ground planes for e.g. analogue and digital processing on the one board. Not to mention high voltage stuff! Ground loop is your friend if you treat it well.
Test house charge excessive amount of money and time to test a board. I'd rather use cheap tools like these to asses my board's EM characteristics.. Thanks for the video Dave and hope you will make more on videos on tackling EM at design phase.. maybe start a new project and show decision making process at each stage of PCB designing..
Thank you very much Dave. Very interesting video! Could you do more EMC video?
Sure!
With 4 layer boards, there's often a much bigger gap between layers 2/3 than between 1/2 and 3/4. But power planes work best when they are tightly coupled with each other. So, assuming you did L2 ground and L3 power, you would have benefited from keeping the copper pours and tying the pour on L1 to power and the pour on L4 to ground. This would increase the interplane capacitance between power and ground significantly, and with proper stitching it would also make it much easier for signals on L4 that reference the power plane to transition to L1 - because the return current can ride along a power pour, instead of searching for a bypass cap so it can switch to referencing ground.
For the truly paranoid, you can put the planes on the outer layers, and it will act like a pseudo strip-line. But in that case you REALLY need to have pours of alternating polarity to the reference plane, because the interplane capacitance will be greatly diminished if your planes are L1 and L4.
Rick Hartley has a lot of very nice videos if you want to explore this topic in more detail.
Need to rewatch when I'm sober.
Didn't help. You?
Coming back two years later to see if there was ever a follow up, cause it was super relevant at the time! Nope. Nothing.
Anyways, my mantra in college became "If you can understand it drunk, you can understand it sober." But to this day, I can only understand Laplace transforms after at least 5 beers
I absolutely would love an emi emc video follow up! I have some testing to do next month
EMC compliance testing isn't always in the far field.
Most of the time it is but some standards test lower frequency H-felds (loop antenna) or E-field (typically 41" dipole antenna) in the near field.
Military and some aviation is famous for this (E-field) however some rail standards as an example test H-field.
Dav is correct about nearfield probes not directly correlating to lab compliance but targeting big peaks or broadband is always worth while prior to hitting the compliance lab.
Just don't forget the cables, sure the emissions are conducted onto a cable however this cable will radiate, potentially greatly.
Great video and demo! Thanks
Rotating the probe is a good tip on passing EMC
Nice, I learnt something today... that’s always a good thing.
14:18 yet another occurrence in the wild of 2pi... it’s too bad that particular paper of Euler’s was used to popularize pi, where he compared semi-circumference to radius (~3.14), instead of one of the ones where he used the full circumference on radius (~6.28). Ah well. At least we’ve now got a name for C/r as well. Hopefully it’ll continue to catch on to a sufficient degree that in another 80 years, few people will remember what pi is... but they’ll know about tau. :) (And for anyone who’s just hearing about this for the first time, see tauday.com.)
With through-hole components, the device leads also connect between the planes so it's not totally dependent on vias.
Yes, but on this board some of them go nowhere.
If you have a pcb with antennas on you will need to internalize those traces and put the GND on the top and bottom.
I wish you would have briefly shown the added GND and VCC planes in the CAD software. It's basically just left up to our imagination about how it looks.
I have a feeling it's a solid copper rectangle, but with with holes everywhere punched through for isolation from the component legs and vias.
For the connections, some kind of thinner traces, usually 4 in a + shape, attaching from the plane to the relevant plated thru holes so the pins can be soldered easier as then the heat isn't wicked away. But without seeing it, as I said, it's left up to our imagination.
That's in the video where I did the layout: ruclips.net/video/Ep4r-wD7PPs/видео.html
Hi Dave, Nice education video and thumbs up. For me, this video has been an eye opener, how layers with power plan make difference in EMC ! Could you pls also let us know, how about having a single layer PCB? - will it generate lower or higher EMC? Any actual comparison please. I usually work with two layers mostly and single layer in some cases.
It gave me a learning to follow the datasheet for the EMC sensitive components, where they recommend to have a separate plan and also no power trace underneath the chips etc. Now I understand it better.
Thank you once again for this video.
Enjoyed this and is nice to revise my Real memory.
Thanks Dave! Awesome video
The 4 layer board shown has the power/ground planes in the middle. What would be the radiated difference if it were reversed, with signals inside, and power/ground outside? I admit that debugging the layout would be terrible, but once it is working, would it make a difference to reverse things?
It will make a difference. I'll try it.
First thing I thought when seeing the layout of the 4 layer board ;-) Will be quite interesting to see the difference it makes! Let's take a wild guess: another 10-15dB?
Expect it will give some improvement as the signal traces will be in a faraday cage. In practice this would be of limited relevance since with SMT the component pads are on the outer layers, and you don’t want to add vias for every signal pin....
Very nice. thanks Dave.
What would happen if you instead of
Horizontal traces
Ground
5V
Vertical traces
you had
Ground
Horizontal traces
Vertical traces
Ground
Would having the ground planes on the outside act as a shield?
I had the same question, it offcorse hide all traces within the board (nightmare to patch or repair), and the 5V will have to bounce a lot between two floatfills areas on layers 2 and 3 I suppose
Signals could interfere more easily
That is common practice for that exact reason. But in this case ditching the power plane for an extra ground plane is a bad idea. From an AC perspective, 5V and GND are the same (thanks to all the decoupling capacitors) so
5V
Horizontal traces
Vertical traces
GND
would be almost as good EMI-wise and make for a much better power distribution network.
There's a book that's generally considered 'the bible' of EMI. It's by a man named Henry w. Ott. In this book he says that this is the best stackup you can have besides using a 12 layer board! Even better than 6 and 8 layer boards!
@@lyfeofajavadevwithfrank9813 Thanks, I found his website. "the two ground planes can be stitched together around the periphery of the board to enclose all the signal traces in a faraday cage. ". NOICE!
www.hottconsultants.com/techtips/pcb-stack-up-2.html
Two of these three problems can be alleviated with the stack-up shown in Fig. 3b, where the two outer planes are ground planes and power is routed as a trace on the signal planes. The power should be routed as a grid, using wide traces, on the signal layers. Two added advantages of this configuration are that; (1) the two ground planes produce a much lower ground impedance and hence less common-mode cable radiation, and (2) the two ground planes can be stitched together around the periphery of the board to enclose all the signal traces in a faraday cage. From an EMC point of view this configuration, if properly done, is the best stack-up possible with a four-layer PCB. Now we have satisfied objectives, (1), (2), (4), and (5) while using only a four-layer board.
_____________ Ground.
_____________ Sig./Pwr.
Figure 3b
_____________ Sig./Pwr.
_____________ Ground
im amazed **my** TTL machine works at all then. my ground planes are split to hell by signal traces with minimal to no stitching, only enough to appease the "unconnected net" rule.
There is often a huge difference between "working" and EMC emissions. It takes a lot to affect 5V TTL logic signals.
Please do more EMC topic videos.
Interesting stuff never really considered that traces basically generate loops, makes sense. I imagine things could get interesting if the signal frequency happens to match the resonant frequency of the loop then it's basically a transmitter. I imagine this is something that has to be accounted for on very sensitive and high frequency systems like computer motherboards.
Yes, that can happen with bypass caps for example, and the results can be terrible.
EMI requirements for devices should be way more strict than they are, the noise floor nowadays is absolutely crazy when you're near civilization
How much of that is EMI versus RF?
@@deelowe3 I'm of course talking about RF, using the term EMI for light and higher frequencies would be a bit silly, even though both are electromagnetic radiation.
@@tommihommi1 I think they meant EMI vs intentional RF radiation
@@RobertSzasz correct
@@RobertSzasz most of it is actually EMI, and most of that EMI is caused by switch mode power supplies.
The efficiency and price is great, but it comes at the cost of a fuckton of EMI when not done perfectly (and it very rarely is done properly)
Oh yes, I want some near field probes, I was going to try and find some, but if you have a diy option that might suit me better.
Yep, will do a video on this shortly.
mmh. I've got an Atari 800XL under my desk, and the shielding on that thing is pretty crazy.
And the thing is, that's the shielding AFTER the FCC relaxed the rules quite substantially.
The original design of these computers were notoriously built like tanks, from really heavy metal casings.
And all of that was to meet FCC compliance.
So... Double layer computer boards huh. XD
Funnily enough though, the Commodore 64 towards the end of it's life was using cardboard with a metal coating for shielding.
The atari never got to that stage, and remained solid metal shielding, but... It's kind of amusing to think what companies did back then to somehow meet the compliance standards AND cut costs to the bone...
Great video Dave, I'm really into PCB cadding at the moment using Eagle 7.5 (Professional) thanks but has anyone noticed you spelt Wavelength wrong? (12:53) DOH! ;)
yeah was going to say; wavelenght
Great video, thanks for this video. Could you make a video about difference in Conduction Emission between 2 layer and 4 layer boards as you use in this video. Use the current probe for the graphics and other connector and LISN 5uH for the power supply and check the Conducted emission up to 200 MHz.
Thanks
@EEVblog what I wonder is . If one would sandwich the the 2 layer traces(original pcb) and make the outside layers a ground-plane (on the 4layers).. would that dampen more? Is there a reason why you went for a ground-plane in the internal layers and not the outside layers? This is actually a thing that I would think makes a difference ( looking at it without knowing the maths ). I love to know where science interferes with my common (miss)conception.
I would have to assume if you redid this with a full ground plane on each of the outside layers, it.would reduce more? May make it a pita for other reasons but.
"Radiated emissions"
"Near field probe"
Make up your bloody mind Dave!
Well, semantics I guess.
They certainly aren't conducted emissions.
Good video. 👏🙌👍👌 😊
Is that an 28C1024 EEPROM? I didn't realise they existed...
Would it be better if there was a ground plane over the top of everything?
Here is an interesting question - would ground filling on a 4 layer board help with EMC? If the clearance from trace to ground fill is smaller than the distance between the outer and inner layers, shouldn't it make a difference?
Just a thought; I don't think you - generally - would be able to get significantly lower inductance and higher capacitance from a flood fill than from an adjacent ground plane. Even though you might get slightly closer to the ground fill with tight tolerances on clearance.
@@mr_gerber Oh yeah, the loop area will be the same. I'm talking about ground pour acting as shielding.
What is the relationship between PCB trace LENGTH and EMC emissions FREQUENCY?
The speed of light in the trace material
@@mr_gerber - The PCB trace acts like an antenna, and , all antennas emit electromagnetic waves at the standing wavelength. The switching digital current generates a wide spectrum of higher frequencies harmonics, the question was by carefully adjusting trace lengths , perhaps some of those EM emissions could be suppressed or entirely eliminated.
Would the program being run and its constantly changing state affect the radiated emissions? Enough to make it pass compliance by having a rom that uses reduced processing power?
In theory, yes. In practice, not really in this case
I'm asking this so it would solve my thirty degree corners
Hey everyone, I need your help. I am currently building SMPS on tl494 chip. But I am little bit confused about kick starting the chip. Can i use 200k resistance between mains 300 volt regulated DC supply and tl494 chip to kick start it with some 22uF cap?? is it safe way to power it up?? I'll power it later on with auxiliary winding with rectification for running the chip continuously. Operating voltage of TL494 is 7 to 40 volt.
Hi Dave, great stuff as always. can advise on an EMI source for testing the performance of a circuit under the electromagnetic field of about 3 V/m in a lab in a range of 80-250mhz?
Sorry, can't off-hand, that's not my field (no pun intended).
@@EEVblog, thanks, anyway, Dave! you're the best!
Makes more sense why a motherboard has like 8 or whatever it has. Plus our FCC regulates along with IEEE, ANSCII, etc. So US Yankees, Lol, get to turn that silly spread spectrum OFF!! Not normally an issue, but for avid overclockers everything makes a difference.
Hey Dave, was this video uploaded (not released) before 29.01.2019 UTC time? I could swear RUclips is using unpublished videos as a source for recommendations, I watched Bil Herd's (from Hackaday) video on PCB Impedance where he explains the relationship between current loop area and magnetic field strength, recommended by RUclips just about 2 days ago...
I uploaded it last night and released to Patrons early.
@@EEVblog Well I can put my tin foil back into the kitchen then... ;)
I am a PCB designer in a small electronics designing company and we are aiming a lot on the low price, so most of thw stuff we do is 2 layer. It caused a lot of problems to us when we go to EMC testing. Biggest problem is the fast switching, you can put 10R to 22R resistor in series in the high speed traces, this helps a lot. Also keep your traces as short as possible and always look for the ground loop.
Yes, it is an excellent idea to put small resistors in series with the IC outputs that drive high speed traces. This helps control the edge rates, reducing radiated emissions. It also reduces the current spikes as the high speed outputs drive the capacitive loading of the traces, vias, and other IC input pins.
The resistors typically allow you to match the impedance of the trace. This stops current sloshing around hence lowering emissions. Think of a wave in a bath of water. Now put some form of blockage in the path and you will see ripples all over. This is what impedance mismatches are. You are trying to make everything look the same to the wave fronts. A better analogy is your tyre across a dirt road and the suspension. Fill in the holes and you creat a smooth surface, or remove dirt piles and create a smooth surface.
@@pentachronic How do you simulate this to know what resistor to add?
@@ZeusandHades You use a Signal Integrity simulator tool. This calculates the impedance of the trace based on the characteristic impedances of the materials of the PCB. Ie using microwave stripline and microstrip modelling. You could do it by hand too (as we did in the old days) using microstrip and stripline formulas (there are books and internet resources - ARRL HAM manual has a lot of info in). Tools such as Altium can do this for you too but for better quality Mentor/Siemens Hyperlynx and Cadence’s Allegro SI package. There’s also Ansoft RF tools too and a few others.
To be more accurate you use IBIS models Io Bus Interface Standard which also models the Inputs and outputs of various ICs on your board. This allows you to simulate the whole signal chain and the trace and figure out the correct termination scheme. I will add that this can be fairly complext to get right if you are working on SerDes or other very fast signalling technologies. It’s a field in it’s own right.
Awesome and quite informative. Thank you.
Uh oh! One board has plastic feet on it, and the other doesn't? Slightly different measurement distance! :D
Well spotted! I can confirm it only makes a slight difference, about 1-2dB tops.
@@EEVblog Thanks for checking! :)
And BTW, it doesn't change the characteristic response shape, just the average amplitude by a small amount.
EEVblog But throughout the video. Both had same general shape, at some distance (you kept mentioning 15dB).
@@EEVblog thats what they all say ;)
@Dave, please take it to an official EMC lab to compare the boards (if a lab would measure it for you for free)
Do you have any opinion regarding the pros and cons of having 4-layer boards with the power-planes as the outer layers and the signal tracks on the inner layers, versus having the signal tracks on the outer layers and the power-planes on the inner layers?
@@MaxWattage
1. Propagation delay is higher for internal layers.
2. You'll need a ton of vias, that would break up the ground/power planes and that wouldn't be great for return paths. Also reducing vias on high speed signals is desirable.
3. It would be difficult to rework the board if needed.
@@EveryThingTechet Points 1 and 3 you are correct. Point 2 is completely wrong. It wouldn't make any difference to the number of vias. You could simply swap the layers but still use the same artwork. You could actually REDUCE the numbers of vias by using blind/buried vias which you can't do with the signal layers on the top and bottom.
@@mrgibbo63me46 nah it really would increase via count. Depending on the board, you could add a ton of vias. Some signal traces wouldn't normally go into the middle or bottom layers, but to make a ground plane on the outside you'd have to add 2 vias per trace.
@@TheRealMonnie Definitely true for an SMD design. Through hole like in this video - the layer orders would not affect via count. You want the power/GND layers to be close together though - increases capacitance between them. There is something to be said for having further GND on additional outer layers and the Faraday shield effect. High speed data is often sandwiched between 2 GND layers to maintain transmission line impedance.
EMC is a myth just ship it
Awesome video! Seeing a side-by-side with identical boards with different layers is something that many of us have never seen done. Quick question: What would the difference be if you reversed the layers and did the traces internally and the ground and 5V externally? Thanks so much for your efforts, Dave!
That would be an interesting experiment.
I guess I just asked this question myself. Would be very interesting
@@EEVblog I would love to see that. Also, what effect does placing a ground "ring" around the outer perimeter of the board that attaches to the device connector shields and then attaches to the board ground plane through capacitors? I know that technique is for ESD protection, but does it help to reduce EMI at all? If you want to see an example of what I'm referring to, you can look at the BeagleBone PCB files. They have that "ground" perimeter on every single layer of the board, not just the outer layers that connect to connector shields. Does that have to do with the high-speed DDR or HDMI signals that are on the board?
Oopps, just asked the same thing.
With a board with 100% through hole components, not much difference except for the better shielding of the signals that now are inside a shielded box (planes on the outer layers). In a board with SMT components it makes a big difference, since having ground/power internal layers means they are almost a complete plane with no voids, while if they are on the outer layers, you have all the pads of the SMT components creating voids and discontinuities in the planes which reduce the effectiveness of the planes. But if you are really concerned with emissions and you have money to spare for a couple of extra layers, you can fill top/bottom layers with ground (only if there is another solid ground internal plane) plus ground ring on the edge of every other layer and use lots of vias on the edges of the PCB to make the PCB like a shielded box for all the signals in the internal layers. Mentor Graphics wrote a book about how using top/bottom layers as ground helps to reduce the number of layers (on board with 16+ layers) since it means bypass caps don't need a via to ground (otherwise every bypass cap has a via to power and one to ground). Also the pair power/ground planes creates a capacitor which is part of the power distribution network to the high speed chips. Changing the position of the power/ground planes in the PCB stackup will change the capacitance and the inductance. FPGA (or other highs speed ICs) companies have lots on apps notes on this topic.
FCC Part 15 is the compliance regs in the US. In the late 70's these new personal computers (Apple II, CP/M systems, but NO IBM PC, yet) plus video game consoles, and other microprocessor based products needed to be added to the compliance standard. So subpart J was added. The whole Part 15 reg has been since realigned, so there is no subpart J anymore. I'm old enough, and had was in the electronics business when subpart J was added. The company gave me the task of making sure our product designs complied with the new regs. Some of these RFI/EMI testing houses are better than others. The first one we went to just ran the test, and we had to fix it back at the shop, before retesting. Another house, let us try things while at their facility, and ran shortened tests to check our intermediate results. They also gave us suggestions. That was a good test facility !
Now products come out of China, and testing boils down to applying a compliance sticker.
Michael Moorrees
No, compliance is still required for foreign products.
Of course testing is still required, but is it actually performed. The thing is when Chinese products are sold directly to customers on websites like eBay, then the testing might be just a sticker. The importing party is responsible for compliance, and when this importing party is a end-user who doesn't know or care about compliance, then the Chinese manufacturer wouldn't bother performing tests. When I have a company importing Chinese electronics and reselling them, then I must be sure they're complaint.
GromBeestje
That’s a downside of importing items. If it has a compliance label then it also has an associated number that you can check. Some stuff I have seen has no compliance at all, or only domestic compliance (which may be tighter in some cases - particularly when you have Trump toadies in charge of compliance).
Retailers are always liable for what they sell, and certainly here items are anonymously bought by compliance authorities and sent to labs for verification. If they don’t comply then the retailer must recall the item(s). I’ve seen it happen with appliances a couple of times, and often with infant and children’s clothing and the like. Regulation is a necessary part of a functional society.
heh. I have a lot of old game consoles and computers around, and it's interesting seeing the progression in the shielding.
Also the history of some designs.
Like the 800XL vs it's predecessor from 4 years earlier.
Mostly the same internal components, but the shielding...
The early 80's variant has some pretty hefty metal shielding inside the plastic outer case...
But the late 70's variant is basically all metal construction with an additional, very thick inner layer of metal just for shielding purposes.
Because at the time it HAD to be to have any hope of meeting compliance standards, yet a few years later near enough the same internal hardware could get away with comparatively flimsy and insubstantial shielding.
(still extremely heavy shielding compared to more modern devices though.)
KuraIthys
It’s more a case of not knowing how to meet the standards, so ensuring compliance by excessive shielding. By the early 1980s it was easier to include EMC compliance testing in the R&D process.
If you decide you want to make a heat map of the emissions, using the Python imaging library (PIL/Pillow) combined with an XY table (to line scan the board) and a way to get the data into a computer would be really neat!
Matplotlib may also work quite well for the application. its easy to use. there is a library called seaborn which is even better for the task.
DaveCAD, now in 3D and augmented reality.
where can I get the update and how much is it? ;-)
Great stuff! I've tried to find information on the internet, but there's so much conflicting information on doing good PCB layout. Videos like this really help. More, please!
How about splitting up four layer board ground for isolating sensitive areas? Can't find any reliable info on how to do it. Some recommend star ground, but I never manage to figure out where to put the center node for best effect. Anyway, thanks again.
look through the texas instruments and analog devices data sheets for their high perormance ADCs and DACs.
Frans de Bruijn Looking in random data sheets for this is going to be hit or miss, as different writers and skill levels will be used from one datasheet to the next.
@@johnfrancisdoe1563 The datasheets often show the component layout with ground isolation for components that have both digital and analog components. T.I. has the board layouts for their evaluation boards available for download, thats a good start to see how they do things. There is also some software called AppCad that you can use for calculating the impedance of tracks if you want to design controlled impedance boards. this is especially important when you are working above 20mhz clock speeds.
The information is conflicting because people try to compress a complicated subject into simple rules of thumb and this rarely works in EMC. As for splitting ground planes, I'd try to avoid it. It can have benefits, but the risks are much bigger and it's full of traps. 9 of 10 times a single uninterrupted ground plane will be best. As for information online, check out Henry Ott's website and the book EMC for product designers.
Great video. A couple of questions:
1) On a 4-layer PCB, is there any significant difference between a SIGNAL-PLANE-PLANE-SIGNAL and a PLANE-SIGNAL-SIGNAL-PLANE arrangement?
2) Are GND+GND and GND+VCC planes equivalent?
My guess is that:
1) PLANE-SIGNAL-SIGNAL-PLANE would be slightly better for radiated EMI because it traps the noise inside the PCB, but that also means it will slightly degrade the signals.
2) Shielding would be equivalent but GND+VCC planes would be better than GND+GND as it lowers the impedance on VCC nets, also the GND+VCC planes would form a wide bypass cap which might help at very high frequencies.
Any thoughts?
edit: Just realized several people came up with the same questions :)
Ah yes, the Gigatron Computer is back. Almost forgot about your 4 layer version. Watching with interest!
Can you make a Video about (pre) compliance testing?
I've done one for conducted mode emissions. I might do another one on mains conducted mode as I have some kit for that. But radiated requires a decent antenna and either an OATS or chamber, or at least something half decent.
@@EEVblog I just passed EMC compliance testing for FCC in north america last weekend. I had some issues with the 200MHz region on my board just over the limit so I tried some bench top probing like in the video with no luck. No matter what I changed, little difference was seen. The issue was the external connections to the PCB were acting as antennas, transmitting trash. A few properly sized ferrites and I was able to obtain one class lower then was the original target.
You were have a common mode radiation problems which is best dealt with by using common mode filters at the point where your signal leaves the PCB
I'd be very interested in the heat map generation idea Dave, give that one a ++
I was thinking about that before he mentioned it, definitely would be neat to setup a rig for that. Kinda like a CNC machine and you put the board in and it just slowly tests each spot. The same rig could perhaps also be used for taking very high res photos of PCBs. Imagine doing something kind of like google maps but with PCBs.
Yes, I was thinking a printable detector for a 3d printer, Dave did say he was going to show how to "roll your own detector" now we could print a clip on case that attaches to a 3d printer head like my creality ender 3 and boom a few hours work and you have a very high spec 3d EMI scanner! the ability to create 3d plots would be of immense use for problematic layouts and great ones too, the ability to log the EMI values in 3d space will lead to all sorts of clever solutions... just a brilliant idea.
It also raises some interesting points too, like getting the DUT to behave in stable consistent way over time, as the scan progresses you don't want the test device changing power levels or turning on and off antennas etc.
What about different sizes (diameters) of vias? Or is it better to use more vias instead?
Both should decrease the impedance.
You missed the *3rd* orientation by having the probe vertical (looking at the video). It might help to determine if a problem is with horizontal left right traces versus vertical up down traces.
... at the 10:55 mark.
Haaaaa the joys of EMI compliance. Love the Tekbox probes I have the same kit with a Siglent SA3021X spectrum analyser, awesome for the price. I also built clamp on RF probes with ferites (Wurth electronics makes great ones) works great to measure radiated emissions from cables and see the difference cable impedance can do. Today there's no reason to not do EMI pre compliance testing in house, it saves a bunch of money and time.
Interesting. FWIW, a coil like that measures the magnetic flux though the coil, so when the coil is flat you're measuring the vertical component of the H field.
Great credit to Dave for going to the effort of making this board and exhibiting the measurements! Some of Dave's videos can be relatively blab or rant oriented, of which there is much on RUclips :-), but videos like the current one really distinguish this channel. Well done Dave!
Great to see A-B-A comparison of the same layout in 2 and 4 layer. Thanks Dave.
EEVblog: EMC, EMI, traces, power rails
ME: b23.tv/zZwnaX
5V 6A, 124 chips from DIP14 to DIP40, no bypass cap at all because there is no room for them at all even for MLCC, thousands of randomly placed signal traces in 3mil or 8mil which of course obviously cannot be routed by hand, you can even hear chips whispering with just a capacitor and an earphone and you can even debug the program with these noises and tell what program it's executing because each piece of program has it's own unique noise, and the most surprising thing is it can work, just with some tiny little small glitches, probably
Would it make a difference if the signal layers were sandwiched in between the supply and ground planes? Wouldn’t they act as outer shielding? Just guessing, sorry for my ignorance
Those plots did not feel like DaveCad stuff. More like DaveLab.
Think it's extra DLC plug-in to get those effects.
This is black magic only because it's very hard to quantify specific causes and effects due to the different nature/characteristics of each circuit. The possible sources for the EMC issue are very well known, however. This video addresses PCB layer aspects of EMC, but the total solution is much more difficult to cover in one video. Check the list below and religiously follow as much as you can. Research each item one by one as time permits. Each item is worth a chapter or two in a textbook. Surprisingly, if you follow these guidelines, then you'll enjoy saying "what EMC problem?" for the rest of your career. It starts at the design stage.
1. One de-cap per power pin, yes per pin not per chip, placed close to the pin(
Nice list, thanks.
Dave! That clip of an anechoic chamber looks exactly like an acoustic anechoic chamber with the sound absorbing wedges. Why would that be needed for radio frequency measurements, or are they different material???
It's a frequency range thing.
I have no clue about electronics. Would a metal Case (grounded)do any positive to Emissions?
Yes, a completely enclosed pcb cannot radiate beyond the enclosure. The problem is that there will always be some openings in an enclosure that allows the emissions to leak out. Or the same emissions couple to wires leaving the board through the enclosure.
Regarding the heatmat, a rather different ("real") kind of heatmap I have seen many years ago in a video (that I can't find):
The guy took some thin layer pcb ground planes (full, with split etc.), painted them black and took some prepreg with signal traces, overlayed them and then ran high power high frequency signals through them. In the end he took an image with a thermal camera. The result was very neatly showing how the low frequency components chose the intuitive shortest path, but the high frequency ones were following the signals, or spreading out in places nobody would have thought of.
i remember being able to hear my Amstrad CPC464 on FM band when loading games!..i guess it was due to be cpc being built as cheap as possable without any sheilding what-so-ever!
A thumbs up from me, but I just had to see this written out: haytch-field.
I love your explanation about near and far field extra to the main subject. When it comes to layers, I newly redesigned an RF board (up to 6 GHz) from 4 to 6 layers. A lot of other changes had to be made, mostly because of the last problems with delivery of the components and because of the heat issue. But I have taken care of the appropriate routing of the RF lines and of grounding in general, in the same time REMOVING many decoupling capacitors (after watching Eric Bogatin presentation at Altium Live) and... the PLL on the board is soooo less noisy!! The biggest Spourious reduced from ca. 30 dBc to less than 50. Sadly I could not compare the grounding alone so nicely as you did
Would be great to have more videos about EMI and EMC, more projects, techniques, measures and recommendations. Thanks for the effort!
it is not simple to think, 4 layes is like a huge capacitor which smooths the rising edge, and that way it lowes the EMC?. I means, two solid middle layer plates, which in parallel with all tracks?.
I've done a video on PCB power planes as a capacitor.
Ground planes are a must for high frequency digital designs, but I was not expecting such a big difference for these low frequency boards. Pretty instructive, thanks for the video!
Hi Dave, many thanks for the valuable contents. I was wondering if you have / intend to do a tutorial on how to route mixed signal boards, how to separate analog and digital Vccs, GNDs planes. Thank you
I LOVE when you do EMC Videos.... My companies units need to be compliant to EN12895 for our systems. I found using a Walkie Talkie is an excellent way to perform some precompliance Radiated Immunity Testing. You should try it out Dave.
If emc is the reason for using a 4 layer board, why not put the signals on the middle two layers? Put the solid power layers on the outside. Yes, you lose some of that free decoupling you would have gotten from sandwiching the power planes closer, but the two layers survived without it, so it's not necessary.
For through hole stuff you can basically for free. But SMD stuff you don't get a free lunch because you'd have to drop vias on every signal.
Thanks for trying this in the follow-up video, Dave!
This was super helpful! Thank you. Short loops, via stitching and watch out for bypass caps. Perfect timing for a current project as well. Still killin' it after all these years!
Yes please on more EMC / EMI videos, especially radiated.
Basically what you can and can't get away with in a design and pass compliance testing. And what you can and can't derive from a semi-affordable pre-compliance testing setup.
Examples of topics I'd love - I'd especially love to see comparisons between lab measurements, DIY antennas and middle road spectrum analyzers like your Siglent and Rigol, DIY OATS , the probes as you did in this video, semi-anechoic chambers, and *especially* with TEM cells since they're supposedly usable in lieu of a proper OATS.
How to properly setup and run the equipment to test against compliance standards for intentional and unintentional radiators.
Good work Dave, amazing video. I have never seen a 2 to 4 layer PCB comparison before, and to have a board for the test with this level of complexity is really a bonus.