#30 How to scroll message on seven segment? ➠ Basys 3 FPGA Board | Verilog HDL

Learn how to display a scrolling message on seven segments. Learn to implement this logic onto an FPGA board using Verilog HDL.
- My Project files (coding) ➤ bit.ly/3xELnXz
- Basys3 Constraint File ➤ bit.ly/2NwgVe3
Table of Contents:
00:05 Introduction/Welcome
01:00 DEMO
02:10 Functional Block Diagram
05:25 Verilog Coding in Vivado
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FPGA PLAYLIST Here: bit.ly/3sYe8LY
RUclips Links:
- Slow Clock ➤ • #6 How to Generate a S... ​
- Binary to BCD Conversion ➤ • #8 Binary to BCD Conve...
- FPGA/Vivado for Beginners ➤ • FPGA for BEGINNERS➟How...
- Scrolling Numbers ➤ bit.ly/3relPy6
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Credit: 👍
- Sound 🎵 : Camtesia
#electronicswithprofmughal #electricalengineering #fpgas #scrollingmessage #electronics

[@ahmetkaanavc8652]

It really worked! I could find it nowhere else. Thanks for the nice tutorial!..

[@ElectronicswithProfMughal]

Thanks Ahmet. Please consider subscribing the channel and share it with your friends.

[@AryanSingh-wu9be]

Hey!! I am getting an error of ambiguous clock in event control..and failed synthesizing module..
Do you know how to resolve it?

[@jogeshsingh854]

Pretty much cool project ,sir👍🏼👍🏼👍🏼

[@ElectronicswithProfMughal]

Thank you Jogesh

[@davorhristov6980]

Hello,
Could you help me I'm trying to synthesize your code but i keep getting an error: [Synth 8-6156]failed synthesizing module Scrolling_Message and [synth 8-91]ambiguous clock in event control[Scrolling_Message.v:98]

[@AryanSingh-wu9be]

I am getting same error, did you resolve it ??

[@shanzagul9243]

Respected Sir! I have a question. Will this code work for displating somthing other than "_HI_".
if I want to display "2020EE51" can I display it by simply editing this code or I will have to add other codes also?

[@ElectronicswithProfMughal]

You’ll have to make changes.

[@shanzagul9243]

@@ElectronicswithProfMughal Thanks a lot Sir. It was very heplful.
I have made changes I hope it works.

[@alperatasoy4926]

Sir i couldn't understand the module part which is the beginning of all codes

[@ElectronicswithProfMughal]

How can I help? Do you have any specific question?

[@alperatasoy4926]

Sir, I thought it was VHDL code but it is Verilog. Do you have VHDL version of this code. If you don't can you help me in terms of finding the source for it or writing the code in VHDL?

[@wagnerolimpiodasilva1223]

Hi, how i get access to the source code?