Excellent tutorial, goes straight to the point. Only thing I would say is missing is talking about "grouping" (of inputs), since collapsed groups are codified into their binary sequences, making it easier to evaluate results. But I'm not even sure if this version already had this, so sorry if I'm mistaken.
If you receive this error: "Error (199013): HDL output file name contains a non-existent directory path" try restore defaults to fix it: Simulation -> Simulation Settings -> Restore Defaults ->Save That worked for me!
Professor Kleitz, I am teaching myself to program FPGAs in Verilog. This video is invaluable for me, I have learnt to simulate systems and it helps be get better understanding of blocking and nonblocking assignments. I am a little confused on the difference (or similarities or the relationship) between a VWF simulation and Modelsim? Its totally possible this is a dumb question when I find out the answer.
Hey, how did you get the vector waveform on v13? I can't find it on mine and people are saying v13 doesn't have support for it starting from v10. So how do you have it on v13? Thanks
When I run functional simulation I dont see new window with waveform, instead I see message below: Error (suppressible): (vsim-12110) All optimizations are disabled because the -novopt option is in effect. This will cause your simulation to run very slowly. If you are using this switch to preserve visibility for Debug or PLI features, please see the User's Manual section on Preserving Object Visibility with vopt. -novopt option is now deprecated and will be removed in future releases. # Error loading design Any suggestions?
I get an error in simulation when I save as any name other than Waveform.vwf, as if it doesn't find the file name when attempting to start the simulation. Is there any reason for that?
This might be a little late, but to fix your problem try going to the waveform editor simulation > simulation options and check the Testbench Generation Command and Netlist Generation Command lines. Go to the very end of both, and change the name "waveform.vwf.vht" to "yourfilename.vwf.vht"
Hi professor, how do I calculate or know the numbers that i should input for the "overwrite clock" ?. I'm trying to figure that out with my vhdl code that I'm still learning on how to do it
hello there. please help me with how to draw the timing diagram when given an input waveform "in general" say a 2-input, 4 input of an AND Gate. i have searched the internet but i cant find help. i will appreciate.
Is it possible to create a more "live" simulation. One where we could switch the values of the inputs and see the output change accordingly. It's a bit of a hassle to have to recreate the entire simulation every time I want to alter one of the values.
I've noticed the simulator always tries the verilog format by default (>> quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog Top)... even if you have VHDL on the EDA Tool Settings in Quartus II. Does anyone know a way to simulate purely VHDL designs? I always end up getting ** Error: (vlog-7) Failed to open design unit file "Top.vo" in read mode, which is due to the fact that my compilation creates Top.vho as it is a VHDL only project.
In this case, offset is the time in seconds that the waveform is delayed before starting it's cycle. For example if your period is one microsecond and you offset one of the waveforms by 0.1 microseconds you'll see that the waveform is delayed by a tenth of a period.
Hey, Bill! I'm using Quartus for academic purposes, and the teacher recommended for us to use the version 13.1 of the software. So, I'm afraid we can't tell yet that it works for the newer versions =\ Anyway, it helped me a lot. Thanks!
Hi sir, Thanks for the wonderful tutorial, will i be able apply different values for the specific input on various time, such as for input A in 2ns, 6ns, 10ns please help me out in this specific problem sir
Thanks for your tutorial, Bill. Like the others, they're helping me learn faster and I appreciate the time you've spent making them.
Thank you for the tutorial! I wish my ECE TA taught me about waveforms like how you did!!
Happy to help!
Excellent tutorial, goes straight to the point.
Only thing I would say is missing is talking about "grouping" (of inputs), since collapsed groups are codified into their binary sequences, making it easier to evaluate results. But I'm not even sure if this version already had this, so sorry if I'm mistaken.
I'm glad you find these tutorials useful. As far as grouping of inputs, you'll see more of that in later chapters like 7, 8, 12, and 13.
If you receive this error: "Error (199013): HDL output file name contains a non-existent directory path" try restore defaults to fix it:
Simulation -> Simulation Settings -> Restore Defaults ->Save
That worked for me!
Well, for some reason not working. it say: "Errors occured during modelism simulation. What to do? Where to find error and how to fix it. THnaks.
Professor Kleitz, I am teaching myself to program FPGAs in Verilog. This video is invaluable for me, I have learnt to simulate systems and it helps be get better understanding of blocking and nonblocking assignments. I am a little confused on the difference (or similarities or the relationship) between a VWF simulation and Modelsim? Its totally possible this is a dumb question when I find out the answer.
sir, how to set the path in EDA tool options... if I perform Run Functional simulation-- shows modelsim altera path not found.. please help sir
What is the difference between this simulation and ModelSim one? When should we use which?
Fajar Suryawan hi fajar , did you find the answer ?
Hey, how did you get the vector waveform on v13? I can't find it on mine and people are saying v13 doesn't have support for it starting from v10. So how do you have it on v13? Thanks
Short and informative, thanks for the video. It really helped me.
When I run functional simulation I dont see new window with waveform, instead I see message below:
Error (suppressible): (vsim-12110) All optimizations are disabled because the -novopt option is in effect. This will cause your simulation to run very slowly. If you are using this switch to preserve visibility for Debug or PLI features, please see the User's Manual section on Preserving Object Visibility with vopt. -novopt option is now deprecated and will be removed in future releases.
# Error loading design
Any suggestions?
Thank you so much. I have been looking for vector waveform alternative on Quartus 13 and this video helped
im getting an error saying "Error: (vsim-3170) Could not find 'work.orgate_vlg_vec_tst'.
#
# Error loading design
Error loading design
Error.
I get an error in simulation when I save as any name other than Waveform.vwf, as if it doesn't find the file name when attempting to start the simulation. Is there any reason for that?
This might be a little late, but to fix your problem try going to the waveform editor simulation > simulation options and check the Testbench Generation Command and Netlist Generation Command lines. Go to the very end of both, and change the name "waveform.vwf.vht" to "yourfilename.vwf.vht"
Dude you just saved my night with this comment. I had no idea how to change the file to make it work. Thank you!!
@@tonykooliyath3325 Thanks a bunch man! You just saved my arse, haha.
There's plenty of samples of basic gate simulations in chapter 4 and 5. They should clear it up for you.
Hi professor, how do I calculate or know the numbers that i should input for the "overwrite clock" ?. I'm trying to figure that out with my vhdl code that I'm still learning on how to do it
hey, did you get to know how to do them?
Thanks for the video, it is just what I needed.
hello there. please help me with how to draw the timing diagram when given an input waveform "in general" say a 2-input, 4 input of an AND Gate. i have searched the internet but i cant find help. i will appreciate.
thank you professor kleitz
You are very welcome
hello... how can I resolve following problem: Error: C:/intelFPGA_lite/20.1/modelsim_ase/win32aloem/vlog failed.
Is it possible to create a more "live" simulation. One where we could switch the values of the inputs and see the output change accordingly. It's a bit of a hassle to have to recreate the entire simulation every time I want to alter one of the values.
Ig you have to write a code for the testing process too?
thanks for the vid, helped me out in my lab
I'm glad it was helpful. Does the fact that the video was produced using version 13 cause any problem?
@@kleitzw I actually use version 13 for my college, so yes!
what will be the grid size and the end time if i have 16 var?
I've noticed the simulator always tries the verilog format by default (>> quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog Top)... even if you have VHDL on the EDA Tool Settings in Quartus II. Does anyone know a way to simulate purely VHDL designs? I always end up getting ** Error: (vlog-7) Failed to open design unit file "Top.vo" in read mode, which is due to the fact that my compilation creates Top.vho as it is a VHDL only project.
How I can visualize variables and signals on the waveform or any other means; thank you
Thank you very much .. Professor Kleitz.
There's no "University Program VWF" option on mine! There are only 3 file options in the Verification Category
Install Version 13 to see the same features shown in the video.
@@BillKleitz I installed version 13.0 and it worked! Thanks!
guys if i have the waveform how can i find the function?
Great tutorial, thanks! I find the simulation workflow in Altera completely unintuitive.
theres not even an option to create that new file in mine!! i need it for tomorrow any chance you could help?
well this is a little late then but, after version 9.1 they got rid of the waveform simulator
Josh P Quartus Version 13.0 and newer has the vector waveform simulation capability as shown in this VideoCast.
Thanks ! Quick and useful video :)
You're welcome!
what does offset mean?? Please explain it to me
In this case, offset is the time in seconds that the waveform is delayed before starting it's cycle. For example if your period is one microsecond and you offset one of the waveforms by 0.1 microseconds you'll see that the waveform is delayed by a tenth of a period.
@@kleitzw you're really my savior
Is there maybe a way to get a truth table for a circuit that has been built on Quartus 13.0?
The easiest way to produce a truth table is with NI MultiSim.
Woah Thanks for the fast reply! And I got NI MultiSim, but I don't know to make a truth table from Quartus to MultiSim. Im kinda new to this program.
what if i use relay to simulate>
Thanks you Professor
Good tutorial, worked for me
Lucas Gomes Dantas
I'm glad to see that this tutorial worked for you I was afraid that the newer version of quartus might have had a few differences.
Hey, Bill! I'm using Quartus for academic purposes, and the teacher recommended for us to use the version 13.1 of the software. So, I'm afraid we can't tell yet that it works for the newer versions =\
Anyway, it helped me a lot. Thanks!
Yeah the text book follows version 13 pretty closely. I hope you get to try the other tutorials too
The main problem is the limited end time to 100us for the simulation. For this reason i still use Quartus V9.
Hi sir, Thanks for the wonderful tutorial, will i be able apply different values for the specific input on various time, such as for input A in 2ns, 6ns, 10ns please help me out in this specific problem sir
Thank you Professor 👍
I try this and it takes forever stuck on top level module on the loading of the functional simulation... RAGE
clear explanation.thank you!
good tut my friend
Sheeeeesh
Thanks a lot sir
You're welcome!
Thanks
Welcome
Muito bom, tudo o que eu queria saber.
c:
Very helpful, thank you.
You're welcome!