Amazing work! I'm new to FPGA-based implementations, and I'm currently working on an FPGA Audio DSP for a university project. I would greatly appreciate it if you could tell me if using your approach would enable me to implement multiple FIR filters on Digilent's Zybo Z7 Development Board (it's based on Xilinx Series 7000 FPGA). Thank you very much!
Hi, yes you can use it, however, for audio, it's better to implement the filters sequentially. Otherwise, you're going to use too many resources. Hope that was helpful.
I believe something is wrong with the HDL. The A registers of the DSP slices are not being inferred (except areg[0], very apparent in your RTL schematic). Am I missing something here?
Yes, I just checked to be sure. What you have found is correct - the RTL will infer only the first areg. I guess Vivado decided the other registers are not needed. Nevertheless, you should get the correct result when you run the implementation.
Thank you for taking your time to create this series. This is GOLD.
I'm glad you find it helpful :)
I've got a dsp exam this friday and I actually understood everything you did here. Very cool, finally the implementation makes sense now too
Thank you, most interesting and inspiring. Will have to watch again to get all the details. Then try a simple filter. 👍👍👍👍
cristal clear, short = great ...
Thank You
Very Understandable video!
Thanks!
Amazing work! I'm new to FPGA-based implementations, and I'm currently working on an FPGA Audio DSP for a university project. I would greatly appreciate it if you could tell me if using your approach would enable me to implement multiple FIR filters on Digilent's Zybo Z7 Development Board (it's based on Xilinx Series 7000 FPGA). Thank you very much!
Hi, yes you can use it, however, for audio, it's better to implement the filters sequentially. Otherwise, you're going to use too many resources. Hope that was helpful.
I believe something is wrong with the HDL. The A registers of the DSP slices are not being inferred (except areg[0], very apparent in your RTL schematic). Am I missing something here?
Yes, I just checked to be sure. What you have found is correct - the RTL will infer only the first areg. I guess Vivado decided the other registers are not needed. Nevertheless, you should get the correct result when you run the implementation.
Can you please give me some applications where we can apply FIR filters of this kind(using the DSP48E1)?
Thanks!
Useful. Thanks!
Great!
can you plz tell how to install coefficient translator?
How can i convert my coefficients to fixed point binary?
Hi, if you're using my coefficient converter, you can select the binary option and the desired bit-width.
How to do this in verilog