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Thank you, most interesting and inspiring. Will have to watch again to get all the details. Then try a simple filter. 👍👍👍👍

I've got a dsp exam this friday and I actually understood everything you did here. Very cool, finally the implementation makes sense now too

Can you please give me some applications where we can apply FIR filters of this kind(using the DSP48E1)?

This is probably the best presented video on multirate processing I've seen. Concise and easy to understand. Great stuff

cristal clear, short = great ... Thank You

VERY GOOD

Thank you for taking your time to create this series. This is GOLD.

Awesome video and great website!

Design and Analysis High Throughput and efficient FIR Filter in dsp so please share your any Contact details sir

Thanks!

Thanks!

Thanks!

Thanks!

These videos are awesome! I'm studying DSP right now and I would like to try these examples on my FPGA. Would be interested in more such videos, and an explanation of your hardware setup :)

How can i convert my coefficients to fixed point binary?

I believe something is wrong with the HDL. The A registers of the DSP slices are not being inferred (except areg[0], very apparent in your RTL schematic). Am I missing something here?

Thanks for this video! Realization and Application of LPF Through FPGA, a webinar organised by DSD, Digital System Design: ruclips.net/video/OWwBluoseck/видео.html

Thanks for this video! Realization and Application of LPF Through FPGA, a webinar organised by DSD, Digital System Design: ruclips.net/video/OWwBluoseck/видео.html

Amazing work! I'm new to FPGA-based implementations, and I'm currently working on an FPGA Audio DSP for a university project. I would greatly appreciate it if you could tell me if using your approach would enable me to implement multiple FIR filters on Digilent's Zybo Z7 Development Board (it's based on Xilinx Series 7000 FPGA). Thank you very much!

Nice series with good explanation. Can't wait to see your next content 🙂

can you plz tell how to install coefficient translator?

Useful. Thanks!

Useful. Thank you.

Very Understandable video! Thanks!

Thanks for the informative tutorial !

Hey, you can use this two functions to convert real values (in your case the coefficients) to fixed point values which makes the code easier to read later since you will have the real coefficient values written in the VHDL code instead of 2's complements. The first one gives you an unsigned output and the second one gives you a signed one, which ever you need. I think the functions are self explanatory but if there is any confusion, let me know. library IEEE_PROPOSED; use IEEE_PROPOSED.FIXED_PKG.ALL; function f_uFixDt ( i_Arg : real ; i_Total_Bits : integer ; i_Fractional_Bits : integer ) return Unsigned is begin return UNSIGNED(to_slv(to_ufixed(i_Arg, i_Total_Bits - i_Fractional_Bits - 1, -i_Fractional_Bits))) ; end function f_uFixDt ; function f_sFixDt ( i_Arg : real ; i_Total_Bits : integer ; i_Fractional_Bits : integer ) return Signed is begin return SIGNED(to_slv(to_sfixed(i_Arg, i_Total_Bits - i_Fractional_Bits - 1, -i_Fractional_Bits))) ; end function f_sFixDt ; Also for testing your system you might wanna simulate it which is a lot easier than real life implementation before you actually go to hardware. I always somehow generate an arbitrary input signal in matlab (also might be the record of a real life signal) and do the fixed point calculations there and when I'm satisfied with the results, I do the same thing on the VHDL side, which is basically giving the input signal we used in matlab (saved on a text file) to the VHDL code in simulation and watching the output or even better, saving the output to a text file and giving it to matlab to compare it to its own output of the first stage we did before. Almost always the output of the matlab and the VHDL should be exactly identical.

Thank you for a nice video. Have you looked into efficient filter structures where the samples are not presented each clock cycle but are presented in blocks of samples (such as 8 or 16 samples at a time), as normally when you have a high sample rate?

Very cool! Have you played around with the underflow / overflow detection? That was one thing that I could never quite wrap my head around. I have recently been playing around with squeezing as much logic out of the DSP48 slices as possible. For example, you could use a single DSP48 to implement most of the ALU functions on a 32-bit softcore CPU (addition, subtraction, logic ops, and result zero testing / comparison). You can also map the inputs to perform dual MACs {A*B+C, A*D+E} simultaneously, if A=7-bits and B,D = 8-bits. Similarly, you can perform true dual MACs {A*B+C, D*E+F} if you restrict A,B,D,E to 5-bits. Those configurations are for unsigned MACs though, I haven't looked at how signed maps (it might cause some weird results with 2's complement spilling over to the upper range).

Thx for the tutorial. Can you please add the tb files to the github folder. Thank you again!

Dimitar many thanks for your tutorials, it is very informative. The same should work with artix a35t right ?

How to do this in verilog

Great!