System Verilog Tutorial 14 | Package in SV | EDA Playground

[@tvprakadeesh7914]

Good bro , keep doing videos like that daily ,it will be very useful to all

[@vlsichaps]

Sure 👍

[@CopyPasteGrow]

when we called the print method, why did you call it as void'(print()) ?
Please explain void'( )

[@gtcontent3069]

Hi sir can you please explain one fsm code

[@Mr.karnatakahacker]

Sure..

[@himanshu6396]

Are package synthesisablle why or why not?

[@vlsichaps]

Packages can contain a mix of synthesizable and non-synthesizable constructs. For example, a package can define data types, constants, functions, tasks, and macros that are synthesizable, as well as non-synthesizable constructs such as assertions, coverage, and debug statements that are only useful for simulation. I hope this helps.
Let us know if any further queries.
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