SYNTHESIZABLE VERILOG

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  • Опубликовано: 15 окт 2024

Комментарии • 7

  • @anushaaenugu941
    @anushaaenugu941 2 года назад +2

    As it is said delays in assignments are non-synthesizable construct but in task FA module delay is used to assign sum

    • @anandjj7731
      @anandjj7731 Год назад

      yeah that fa is not synthesizable because of that lol

  • @dhrubajyotimandal
    @dhrubajyotimandal 9 месяцев назад

    why do we have built in primitives? while we can already implement things behaviorally like "assign x=a|b;" instead of "or (x,a,b);"? does those primitives serve some different purpose?

  • @dileepnaidu3850
    @dileepnaidu3850 10 месяцев назад

    What is the difference between a task and a module?

  • @OpaQueue
    @OpaQueue Год назад

    for loop is synthesizable?

  • @dhrsajghelani9862
    @dhrsajghelani9862 3 года назад +1

    Very good prof

  • @prasanthbadisa
    @prasanthbadisa 7 лет назад +1

    try to show the results using software