Advanced Process Technologies - Part 3: FinFET Layout
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- Опубликовано: 2 июл 2024
- This is part 3 of my lecture on Advanced Process Technologies.
In this lecture, I introduce advanced process technologies based on FinFET (Tri-gate) structures. In the lecture, I start with the motivation for the move to the "third-dimension" and then overview the primary mechanisms for fabricating a deeply scaled (22nm and below) FinFET device in comparison with traditional planar device fabrication. This leads to the perspective of FinFETs from a designers point of view, taking a look at the features of these new devices and process nodes and focusing on transistor layout, layout-dependent effects (LDEs) and device parasitics. I wrap up my talk with a look to the near-future with the current trends of gate-all-around (GAA) nano-sheet (nano-ribbon) devices and buried power rails.
Many thanks to Alvin Loke for his great tutorials on these subjects in recent years and Or Nahum, who taught me a lot about the process aspects of deep nanoscale fabrication.
The lecture slides, along with the slides and links to videos for many other lectures, can be found on the EnICS Labs website at enicslabs.com/short-courses/
All rights reserved:
Prof. Adam Teman
Emerging nanoscaled Integrated Circuits and Systems (EnICS) Labs
Faculty of Engineering, Bar-Ilan University
Thank you so much. As a PD engineer this helped me a lot in understanding FINFETs. The graphics, the explanation, the flow of information was just perfect
Glad it helped!
Sir Classic Explanation of layout. Thank you so much for your hard work and effort .. to make things so simple to understand.
You are most welcome
So far, this is one of the highest-quality courses I have ever seen for FinFET. Really happy to find your video. We are eager to learn!! Please feed us more :)
Wow, thanks!
Hopefully I will find time to prepare some new videos this semester!
Sir, thanks a lot, I'm currently working at advanced packaging area. Your video helps me understand FEOL a lot!
Great!
Thank you so much the detailed explanation
You are welcome!
Excellent content. Thumbs up
Much appreciated!
@@AdiTeman keep up the great work. Subscribed your channel 👍
excellent lecture
Thanks
Thank you for the good lecture. It was very helpful.
Could you tell me about the question below?
1. What is the purpose of using the "gate cut layer" in the 14nm process? In my understanding, the gate cut layer also plays a role in separating the gate area of TR from other TRs.
You said that dummy gate pc also separates the active region, but I would like to know the difference.
2. When layout, is the big difference between 14nm and 10nm about "COAG"? (deleted , I'm sorry I asked you a question)
3. Could you make a detailed lecture on layout of GAA? I haven't experienced this process yet, so I'm very interested.
Have a nice day :)
Should I think that "gate cut layer" is seperating "poly" , and dummy gate is seperating active area like STI by cutting "fin" ?
Hi,
I'm not exactly sure I will answer accurately, since you are using different naming conventions than I used in the lecture. But in general, if I understand what you're asking, cut layers are used as follows:
1) draw a very regular pattern with really tight design rules (such as fins or poly-gates)
2) use a second mask with more relaxed design rule that just etches away the feature we just made in the perpendicular direction.
So if we have a long poly that is very close to its neighbor using all kinds of tough fabrication tricks (like SAQP), then we can separate different gates of different transistors by making cuts at a resolution that I can do with "standard" photolithography.
Therefore, for each "really tight" layer, you often have a cut layer.
Regarding your question about COAG in 14nm vs. 10nm processes - I actually have no idea. Unfortunately, I don't have access to these design kits (I'm guessing, from Intel) and so I can't even try to figure it out... To be honest, I don't even know what process this was introduced at by each foundry other than according to rumors or not-necessarily accurate internet searches...
The same can be said about GAA. All I know so far is what I've seen other people publish and discuss. If and when I have the opportunity to get a more deep understanding, I will be excited to teach about it!
@@AdiTeman Thank you very much for your reply.
I've always been curious about the cut layer, but I understood what you told me.
The explanation "really tight layer" completely solved what I was curious about.
Right, the process is very, very secretive. I forgot for a moment ;)
The lecture you taught was very helpful. I look forward to good lectures in your Channel
Thank you!! :)
Well done. In 9:16 what is meant by 'Here we have VG which is a *coag* '?
A COAG is "contact over active gate".
This is an optimization introduced, I think, in Intel's 10nm process, where the contact is applied on top of the transistor channel, as opposed to pulling the poly gate off of the channel and dropping the contact on top of this extension.
@@AdiTeman Thanks!!