Advanced Process Technologies - Part 4: Layout Dependent Effects and Parasitics

This is part 4 of my lecture on Advanced Process Technologies.
In this lecture, I introduce advanced process technologies based on FinFET (Tri-gate) structures. In the lecture, I start with the motivation for the move to the "third-dimension" and then overview the primary mechanisms for fabricating a deeply scaled (22nm and below) FinFET device in comparison with traditional planar device fabrication. This leads to the perspective of FinFETs from a designers point of view, taking a look at the features of these new devices and process nodes and focusing on transistor layout, layout-dependent effects (LDEs) and device parasitics. I wrap up my talk with a look to the near-future with the current trends of gate-all-around (GAA) nano-sheet (nano-ribbon) devices and buried power rails.
Many thanks to Alvin Loke for his great tutorials on these subjects in recent years and Or Nahum, who taught me a lot about the process aspects of deep nanoscale fabrication.
The lecture slides, along with the slides and links to videos for many other lectures, can be found on the EnICS Labs website at enicslabs.com/short-courses/
All rights reserved:
Prof. Adam Teman
Emerging nanoscaled Integrated Circuits and Systems (EnICS) Labs
Faculty of Engineering, Bar-Ilan University

[@sagarkore9648]

Just one word sir awesome :)

[@AdiTeman]

Thank you! Cheers!

[@minaminisuwaruya]

Thanks a lot !!!!

[@AdiTeman]

You're welcome!

[@akhilabhat5562]

Any way to get this videos in English language?