Hi Sir, I am really fortunate to watch your videos for understanding the concepts in SERDES. Your videos are very simple to understand the blocks, their requirements and functionality. Thanks a lot for your videos.
Thanks for the presentation. I got one question: why is the DFE immune to noise and crosstalk. Noise and crosstalk will be present in the input of DFE, how could DFE know how to make the decision?
Hi Minh, Nice to meet you, and thank you for your great question. The DFE would not be immune to noise & crosstalk, but at least the DFE would not amplify it. For those noise & crosstalk are mostly high-frequency content, and the CTLE would amplify it (at the frequency greater than the Nyquist rate) and de-emphasize the DC content and reduce the SNR. So, the DFE would be less vulnerable to noise & crosstalk than the CTLE.
Hi Dr.Cheng, thanks for the great video. I'd like to inquire one question which is the tap, can I take tap as a filter since if DFE have more taps, it means DFE can cancel more post-cursor ISI and if FFE has more tpas, it can cancel more pre-cursor ISI, and if we increase more tpas, it means we need more flip-flps, so it will increase the area. Please correct me if I'm wrong. Thank you again.
Thanks for the video. I have a question. The minimum amount of Swing at the Slicer input is decided by "BER/Slicer input noise/Sensitivity/offset" ? What limits the max side? Can we have very High Swing at the Slicer input for both High and low frequency components of the signal? @1:40 : You tell for less dynamic range , sampling accuracy be increased or clockJitter power requirement is reduced? Can you explain in some more detail?
Hi SUMAN, Thanks for the good questions. I have comments below. Thanks for the video. I have a question. The minimum amount of Swing at the Slicer input is decided by "BER/Slicer input noise/Sensitivity/offset" ? What limits the max side? Can we have very High Swing at the Slicer input for both High and low frequency components of the signal? [CC] The maximum swing may distort the linearity of the summing amplifier and then the DFE might not work well. In addition, there's a reliability issue if the maximum swing was not considered in the design. @1:40 : You tell for less dynamic range , sampling accuracy be increased or clockJitter power requirement is reduced? Can you explain in some more detail? [CC] The less dynamic range may help mitigate the sampler's hysteresis and perform faster with a less clock to Q or input setup time. Then the clock requirements of the sampler can be reduced. Thanks, CC
Thanks for your video, I have a question for the eye diagram at 8:17. Is the green eye diagram what we want to have, such that at the clock rising edge, there are 4 different levels? But the input has only 2 levels, so I am confused why the green one is better than the red one. Thanks!
Hi Hanyue, Nice to meet you. Thank you so much for the good question. The example I've shown here is a half-rate DFE topology; therefore, the rising edge of the clock would sample the 2 levels eye diagram while the 4 different levels eye diagram was settled in the summing nodes. Hopefully, this helps your understanding. Thanks again.
@vars008rcb nice to meet you. Thanks and I'm glad you liked it. The FFE would decrease the DC swing and boot the high frequency (most noise content), so the high-frequency noise is equivalently amplified.
Hi sir, thanks for the sharing amazing video. I'm wondering why DFE only cancel the post cursor(signal falling edge) due to at next bit may create nonzero value? No impact of pre cursor(signal rising edge) if the nonzero value is negative?
@顏擇敏 Thanks for the good question. The DFE is decision feedback to cancel the previous bit (symbol); therefore, that only canceled the previous bit's post-cursor. Technically, the DFE cannot cancel the previous bit's pre-cursor.
Thank you very much for your great videos. Just a dull question, would you please explain, why a bumpy response would create a reflected waveform time domain? And why they are created in 3UI, 6UI and so on?
Thanks for the feedback and good question. The case study of those reflections was just an example of 3UI, 6UI, and so on, which might not be in other cases. The reflections may be from the discontinuities in the packages, vias, connectors, etc. So, every link could have different reflections in time so as the response in the frequency domain. Lastly, not the bumpy response creates a reflected waveform. The discontinuities at the interface would create a reflected waveform and the bumpy response was just the frequency response due to the discontinuities.
Very good channel , liked and subscribed! Two questions. 1) Is the DFE a FIR filter ? like TXFFE. 2) I imagine that DFE has a high pass frequency response but with bumps. While in your TXFFE video, frequency response of the TXFFE is more similar to CTLE (no bumps). This is surprising, because it seems to me that TXFFE and DFE are very similar to each other... Thanks
@Hrachya Khachatryan Thanks for the feedback and I'm glad you liked it. I have comments below. 1) No, it's like an IIR since the feedback tap 2) Both TXFFE & DFE are discrete-time, but both TXFFE & CTLE will amplify the noise, but the DFE wouldn't; therefore, the similarity is still different in terms of properties :)
Thanks for the video, I have a question about DFE error propagation. How do we ensure DFE error propagation doesn't make compliance test fail ? Is there any "simple" method to evaluate it?
Hi Jimmy, nice to meet you and thank you so much for the excellent question. I'll make the compliance test video for the "PCIe" & "10GKR" or others to elaborate on that. :)
Very nicely put presentations and I learnt something new! At 6:40 you mentioned that propagation error is usually not a big issue. As the speed increases, closing the timing of the first tap could be difficult due to many number of taps being implemented at the summing node. I am wondering what's your thoughts about the error propagations due to the difficulties of closing the first tap at high speed design? Appreciate it. Thanks again!
Thanks for the feedback and good question. You could apply a sliding tap or separate summing amplifier to reduce the loading for the 1st tap at a high-speed SerDes. Let me know if that's not clear to you and I could make another video to emphasize what I meant.
@@circuitimage Yes that would be something interesting to learn about(regarding the tricks to reduce capacitive loading on the summing node)! Look forward to it!
Hi Teacher, I have been enjoying your videos. Thanks! I have some question. It seems the DFE can reduce the ISI by suppressing the post cursor, where educing the ISI can improve the Voltage margin, that is the eye height, correct? Does DFE improves eye width? It seems to me both CTLE and DFE improves eye height only, Is there any receiver parameters can improve eye width especially the eye left and right are not equal/balance?
Hi Zan, nice to meet you and I'm glad you like my videos. Thank you so much for the excellent questions. Please be advised that both the eye width (EW) and eye height (EH) are correlated; therefore, if EH is improved, the EW should be improved. But for DFE, there's a subtlety since that would require feedback (FB) timing or settling time requirement and most of the data DFEs cannot FB fast enough, so that's not improving the EW effectively. I can show other edge DFEs images later, and that would help the EW effectively.
@@ZanZ-qi6wz Thank you so much for the good questions. If the eye width was shifted, you could check if the TXFFE or CTLE did not cancel the pre-cursor well enough. Another possibility is the DFE's settling time takes too long, even though it meets the 1UI timing. :)
The number of taps means how many Tbit (or UI) you can cancel the length of the ISI. For example, if you only have 2 taps DFE, you can only cancel the 1st & 2nd post-cursor by the 1st tap & 2nd tap feedback summing signalling to cancel the previous ISI; therefore, you cannot cancel the previous 10 UI's ISI, for example.
@@circuitimage Understood. Is there an article or link that explains how to configure taps for DFE in detail? Also, do you have an email ID for further question?
Really helpful！Since SerDes is a rare topic in school, it is hard for me to start from the begining. I've learned a lot through the videos, thx.
Hi Po-Yao, nice to meet you. I'm glad you learned a lot. Thank you for your feedback and hopefully, we could meet one day in Taiwan. 😀😀😀
Hi Sir, I am really fortunate to watch your videos for understanding the concepts in SERDES. Your videos are very simple to understand the blocks, their requirements and functionality. Thanks a lot for your videos.
Thanks for the feedback and please share w/ someone may benefit from it.
Thanks for the presentation.
I got one question: why is the DFE immune to noise and crosstalk. Noise and crosstalk will be present in the input of DFE, how could DFE know how to make the decision?
Hi Minh, Nice to meet you, and thank you for your great question. The DFE would not be immune to noise & crosstalk, but at least the DFE would not amplify it. For those noise & crosstalk are mostly high-frequency content, and the CTLE would amplify it (at the frequency greater than the Nyquist rate) and de-emphasize the DC content and reduce the SNR. So, the DFE would be less vulnerable to noise & crosstalk than the CTLE.
@@circuitimage thanks for clarifying. Keep up the great content. 👍🏻
@@MinhPham-je1gt Sure. Thanks again for your great feedback.
@@MinhPham-je1gt Sure. Will do and I hope to receive more great feedback from you :)
Hi Dr.Cheng, thanks for the great video.
I'd like to inquire one question which is the tap, can I take tap as a filter since if DFE have more taps, it means DFE can cancel more post-cursor ISI and if FFE has more tpas, it can cancel more pre-cursor ISI, and if we increase more tpas, it means we need more flip-flps, so it will increase the area. Please correct me if I'm wrong.
Thank you again.
Thank you so much for your good questions. Your understanding is correct and we can.
@@circuitimage Thanks for your reply
You are very welcome 🤗
Thanks for the video. I have a question. The minimum amount of Swing at the Slicer input is decided by "BER/Slicer input noise/Sensitivity/offset" ? What limits the max side? Can we have very High Swing at the Slicer input for both High and low frequency components of the signal?
@1:40 : You tell for less dynamic range , sampling accuracy be increased or clockJitter power requirement is reduced? Can you explain in some more detail?
Hi SUMAN,
Thanks for the good questions. I have comments below.
Thanks for the video. I have a question. The minimum amount of Swing at the Slicer input is decided by "BER/Slicer input noise/Sensitivity/offset" ? What limits the max side? Can we have very High Swing at the Slicer input for both High and low frequency components of the signal?
[CC] The maximum swing may distort the linearity of the summing amplifier and then the DFE might not work well. In addition, there's a reliability issue if the maximum swing was not considered in the design.
@1:40 : You tell for less dynamic range , sampling accuracy be increased or clockJitter power requirement is reduced? Can you explain in some more detail?
[CC] The less dynamic range may help mitigate the sampler's hysteresis and perform faster with a less clock to Q or input setup time. Then the clock requirements of the sampler can be reduced.
Thanks,
CC
Thanks for your video, I have a question for the eye diagram at 8:17. Is the green eye diagram what we want to have, such that at the clock rising edge, there are 4 different levels? But the input has only 2 levels, so I am confused why the green one is better than the red one. Thanks!
Hi Hanyue,
Nice to meet you. Thank you so much for the good question. The example I've shown here is a half-rate DFE topology; therefore, the rising edge of the clock would sample the 2 levels eye diagram while the 4 different levels eye diagram was settled in the summing nodes. Hopefully, this helps your understanding.
Thanks again.
Hi Chen, nice videos! could you please explain how FFE has noise amplification problem?
@vars008rcb nice to meet you. Thanks and I'm glad you liked it. The FFE would decrease the DC swing and boot the high frequency (most noise content), so the high-frequency noise is equivalently amplified.
@@circuitimage Thanks for the quick response. It makes sense!
@@vars008rcb You're very welcome :)
@@vars008rcb Thanks for confirming my mental model of the FFE image as well. :)
Hi sir, thanks for the sharing amazing video. I'm wondering why DFE only cancel the post cursor(signal falling edge) due to at next bit may create nonzero value? No impact of pre cursor(signal rising edge) if the nonzero value is negative?
@顏擇敏 Thanks for the good question. The DFE is decision feedback to cancel the previous bit (symbol); therefore, that only canceled the previous bit's post-cursor. Technically, the DFE cannot cancel the previous bit's pre-cursor.
Thank you very much for your great videos. Just a dull question, would you please explain, why a bumpy response would create a reflected waveform time domain? And why they are created in 3UI, 6UI and so on?
Thanks for the feedback and good question. The case study of those reflections was just an example of 3UI, 6UI, and so on, which might not be in other cases. The reflections may be from the discontinuities in the packages, vias, connectors, etc. So, every link could have different reflections in time so as the response in the frequency domain. Lastly, not the bumpy response creates a reflected waveform. The discontinuities at the interface would create a reflected waveform and the bumpy response was just the frequency response due to the discontinuities.
Very good channel , liked and subscribed!
Two questions.
1) Is the DFE a FIR filter ? like TXFFE.
2) I imagine that DFE has a high pass frequency response but with bumps. While in your TXFFE video, frequency response of the TXFFE is more similar to CTLE (no bumps). This is surprising, because it seems to me that TXFFE and DFE are very similar to each other...
Thanks
@Hrachya Khachatryan Thanks for the feedback and I'm glad you liked it. I have comments below.
1) No, it's like an IIR since the feedback tap
2) Both TXFFE & DFE are discrete-time, but both TXFFE & CTLE will amplify the noise, but the DFE wouldn't; therefore, the similarity is still different in terms of properties :)
@@circuitimage Thank you )))
@@hrachya_khachatryan You're very welcome :)
Thanks for the video, I have a question about DFE error propagation. How do we ensure DFE error propagation doesn't make compliance test fail ? Is there any "simple" method to evaluate it?
Hi Jimmy, nice to meet you and thank you so much for the excellent question. I'll make the compliance test video for the "PCIe" & "10GKR" or others to elaborate on that. :)
Very nicely put presentations and I learnt something new! At 6:40 you mentioned that propagation error is usually not a big issue. As the speed increases, closing the timing of the first tap could be difficult due to many number of taps being implemented at the summing node. I am wondering what's your thoughts about the error propagations due to the difficulties of closing the first tap at high speed design? Appreciate it. Thanks again!
Thanks for the feedback and good question. You could apply a sliding tap or separate summing amplifier to reduce the loading for the 1st tap at a high-speed SerDes. Let me know if that's not clear to you and I could make another video to emphasize what I meant.
@@circuitimage Yes that would be something interesting to learn about(regarding the tricks to reduce capacitive loading on the summing node)! Look forward to it!
@Zheng Lai :) Here you go: ruclips.net/video/BZLVH-8JFys/видео.html
Hi Teacher, I have been enjoying your videos. Thanks! I have some question. It seems the DFE can reduce the ISI by suppressing the post cursor, where educing the ISI can improve the Voltage margin, that is the eye height, correct? Does DFE improves eye width? It seems to me both CTLE and DFE improves eye height only, Is there any receiver parameters can improve eye width especially the eye left and right are not equal/balance?
Hi Zan, nice to meet you and I'm glad you like my videos. Thank you so much for the excellent questions. Please be advised that both the eye width (EW) and eye height (EH) are correlated; therefore, if EH is improved, the EW should be improved. But for DFE, there's a subtlety since that would require feedback (FB) timing or settling time requirement and most of the data DFEs cannot FB fast enough, so that's not improving the EW effectively. I can show other edge DFEs images later, and that would help the EW effectively.
@@circuitimage Thank you teacher! another question. If I see the eye width is horizontally shift left / right side, Which parameter I should check?
@@ZanZ-qi6wz Thank you so much for the good questions.
If the eye width was shifted, you could check if the TXFFE or CTLE did not cancel the pre-cursor well enough. Another possibility is the DFE's settling time takes too long, even though it meets the 1UI timing. :)
@@circuitimage Thank you very much for your explanation again! Very helpful!
@@ZanZ-qi6wz You are very welcome. :)
Just saying thanks for this , thank you so much
Thanks for the feedback and please share w/ someone may benefit from it.
What is the meaning of taps in DFE? (1 tap, 2 tap, 3 tap etc)
The number of taps means how many Tbit (or UI) you can cancel the length of the ISI. For example, if you only have 2 taps DFE, you can only cancel the 1st & 2nd post-cursor by the 1st tap & 2nd tap feedback summing signalling to cancel the previous ISI; therefore, you cannot cancel the previous 10 UI's ISI, for example.
@@circuitimage Understood. Is there an article or link that explains how to configure taps for DFE in detail? Also, do you have an email ID for further question?
Very well explain. Thx you
Hi boon, nice to meet you and thank you for your feedback. I'm glad that helped. 😊
Jacobson Walks
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Hi Melissa, nice to meet you and thank you for feedback. :)
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